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DEVICES
=======
Table of contents
1. Introduction
2. Linear Devices
2.1 CAP - Linear capacitor
2.2 IND - Linear inductor
2.3 RES - Linear resistor
2.4 R, L, C behavioral (non-linear) devices
3. Distributed Elements
3.1 CPL - Simple Coupled Multiconductor Lines (Kspice)
3.2 LTRA - Lossy Transmission line
3.3 TRA - Transmission line
3.4 TXL - Simple Lossy Transmission Line (Kspice)
3.5 URC - Uniform distributed RC line
4. Voltage and current sources
4.1 ASRC - Arbitrary Source
4.2 CCCS - Current Controlled Current Source
4.3 CCVS - Current Controlled Voltage Source
4.4 ISRC - Independent Current Source
4.5 VCCS - Voltage Controlled Current Source
4.6 VCVS - Voltage Controlled Voltage Source
4.7 VSRC - Independent Voltage Source
5. Switches
5.1 CSW - Current controlled switch
5.2 SW - Voltage controlled switch
6. Diodes
6.1 DIO - Junction Diode
7. Bipolar devices
7.1 BJT - Bipolar Junction Transistor
7.2 VBIC - Bipolar Junction Transistor
7.3 HICUM2 - Bipolar High Speed Junction Transistor
8. FET devices
8.1 JFET - Junction Field Effect transistor
9. HFET Devices
9.1 HFET1 - Heterostructure Field Effect Transistor Level 1
9.2 HFET2 - Heterostructure Field Effect Transistor Level 2
10. MES devices
10.1 MES - MESFET model
10.2 MESA - MESFET model (MacSpice3f4)
11. MOS devices
11.1 MOS1 - Level 1 MOS model
11.2 MOS2 - Level 2 MOS model
11.3 MOS3 - Level 3 MOS model
11.4 MOS6 - Level 6 MOS model
11.5 MOS9 - Level 9 MOS model
11.6 BSIM1 - BSIM model level 1
11.7 BSIM2 - BSIM model level 2
11.8 BSIM3 - BSIM model level 3 vers. 0
11.9 BSIM3 - BSIM model level 3 vers. 1
11.10 BSIM3 - BSIM model level 3 vers. 2
11.11 BSIM3 - BSIM model level 3 vers. 3
11.12 BSIM4 - BSIM model level 4
11.13 HiSIM2 - Hiroshima-University STARC IGFET Model
11.14 HiSIM_HV - Hiroshima-University STARC IGFET High Voltage Model
11.15 VDMOS - A simple PowerMOS transistor model derived from MOS1
12. SOI devices
12.1 BSIM3SOI_FD - SOI model (fully depleted devices)
12.2 BSIM3SOI_DD - SOI Model (dynamic depletion model)
12.3 BSIM3SOI_PD - SOI model (partially depleted devices)
12.4 BSIMSOI - SOI model (partially/full depleted devices)
12.5 SOI3 - STAG SOI3 Model
13. Verilog-A models
14. XSPICE code models
15. Digital Building Blocks (U instances)
------------------
1. Introduction
This file contains the status of devices available in ngspice. This file
will be updated every time the device specific code is altered or changed to reflect the current status of this important part of the simulator
2. Linear Devices
2.1 CAP - Linear capacitor
Ver: N/A
Class: C
Level: 1 (and only)
Dir: devices/cap
Status:
Enhancements over the original model:
- Parallel Multiplier
- Temperature difference from circuit temperature
- Preliminary technology scaling support
- Model capacitance
- Cj calculation based on relative dielectric constant
and insulator thickness
2.2 IND - Linear Inductor
Ver: N/A
Class: L
Level: 1 (and only)
Dir: devices/ind
Status:
Enhancements over the original model:
- Parallel Multiplier
- Temperature difference from circuit temperature
- Preliminary technology scaling support
- Model inductance
- Inductance calculation for toroids or solenoids
on the model line.
2.3 RES - Linear resistor
Ver: N/A
Class: R
Level: 1 (and only)
Dir: devices/res
Status:
Enhancements over the original model:
- Parallel Multiplier
- Different value for ac analysis
- Temperature difference from circuit temperature
- Noiseless resistor
- Flicker noise
- Preliminary technology scaling support
2.4 R, L, and C behavioral (non-linear) devices
Their values are determined by an expression (equation)
which may contain a combination of voltage and current
sources embedded in a mathematical function.
3. Distributed elements
3.1 CPL - Simple Coupled Multiconductor Lines (Kspice)
Ver: N/A
Class: P
Level: 1 (and only)
Dir: devices/cpl
Status:
This model comes from swec and kspice. It is not documented, if
you have kspice docs, can you write a short description
of its use ?
- Does not implement parallel code switches
- Probably a lot of memory leaks
Enhancements over the original model:
- Better integrated into ngspice adding CPLask, CPLmAsk and
CPLunsetup functions
3.2 LTRA - Lossy Transmission line
Ver: N/A
Class: O
Level: 1 (and only)
Dir: devices/ltra
Status:
- Original spice model.
- Does not implement parallel code switches.
3.3 TRA - Transmission line
Ver: N/A
Class: T
Level: 1 (and only)
Dir: devices/tra
Status:
- Original spice model.
- Does not implement parallel code switches.
3.4 TXL - Simple Lossy Transmission Line (Kspice)
Ver: N/A
Class: Y
Level: 1 (and only)
Dir: devices/txl
Status:
This model comes from kspice. It is not documented, if
you have kspice docs, can you write a short description
of its use ?
There is some code left out from compilation:
TXLaccept and TXLfindBr. Any ideas ?
- Does not implement parallel code switches
3.5 URC - Uniform distributed RC line
Ver: N/A
Class: U
Level: 1 (and only)
Dir: devices/urc
Status:
- Original spice model.
- Does not implement parallel code switches.
4. Voltage and current sources
4.1 ASRC - Arbitrary Source
Ver: N/A
Class: B
Level: 1 (and only)
Dir: devices/asrc
Status:
4.2 CCCS - Current Controlled Current Source
Ver: N/A
Class: F
Level: 1 (and only)
Dir: devices/cccs
Status:
- Original spice model.
4.3 CCVS - Current Controlled Voltage Source
Ver: N/A
Class: H
Level: 1 (and only)
Dir: devices/ccvs
Status:
- Original spice model.
4.4 ISRC - Independent Current Source
Ver: N/A
Class: I
Level: 1 (and only)
Dir: devices/isrc
Status:
This is the original spice device improved by Alan Gillespie
with the following features:
- Source ramping
- Check for non-monotonic series in PWL
4.5 VCCS - Voltage Controlled Current Source
Ver: N/A
Class: G
Level: 1 (and only)
Dir: devices/vccs
Status:
- Original spice model.
4.6 VCVS - Voltage Controlled Voltage Source
Ver: N/A
Class: E
Level: 1 (and only)
Dir: devices/vcvs
Status:
- Original spice model.
4.7 VSRC - Independent Voltage Source
Ver: N/A
Class: V
Level: 1 (and only)
Dir: devices/vsrc
Status:
The original spice device improved with the following features:
- Source ramping
- Check for non-monotonic series in PWL
- Random values
- White, 1/f, and random telegraph transient noise sources
5. Switches
5.1 CSW - Current controlled switch
Ver: N/A
Class: W
Level: 1 (and only)
Dir: devices/csw
Status:
- This model comes from Jon Engelbert.
5.2 SW - Voltage controlled switch
Ver: N/A
Class: S
Level: 1 (and only)
Dir: devices/sw
Status:
- This model comes from Jon Engelbert.
6. Diodes
6.1 DIO - Junction Diode
Ver: N/A
Class: D
Level: 1 (and only)
Dir: devices/dio
Status:
Enhancements over the original model:
- Parallel Multiplier
- Temperature difference from circuit temperature
- Forward and reverse knee currents
- Periphery (sidewall) effects
- Temperature correction of some parameters
- Self heating
7. Bipolar devices
7.1 BJT - Bipolar Junction Transistor
Ver: N/A
Class: Q
Level: 1
Dir: devices/bjt
Status:
Enhancements over the original model:
- Parallel Multiplier
- Temperature dependency on rc,rb,re
- Temperature difference from circuit temperature
- Different area parameters for collector, base and emitter
- Support lateral PNP
7.2 VBIC - Bipolar Junction Transistor
Ver: N/A
Class: Q
Level: 4 & 9
Dir: devices/vbic
Status:
This is the Vertical Bipolar InterCompany model in version 1.2. The author
of VBIC is Colin McAndrew mcandrew@ieee.org.
Spice3 Implementation: Dietmar Warning DAnalyse GmbH
Web Site: http://www.designers-guide.com/VBIC/index.html
Notes: This is the 4 terminals model, without excess phase and thermal
network.
7.3 HICUM 2 - Bipolar Junction Transistor for high frequency
Ver: 2.4
Class: Q
Level: 8
Dir: devices/hicum2
HICUM: HIgh CUrrent Model is a physics-based geometry-scalable compact
model for homo- and heterojunction bipolar transistors, developed by
the HICUM Group at CEDIC, University of Technology Dresden, Germany.
Web Site: https://www.iee.et.tu-dresden.de/iee/eb/hic_new/hic_intro.html
8. FET devices
8.1 JFET - Junction Field Effect transistor
Ver: N/A
Class: J
Level: 1
Dir: devices/jfet
Status:
This is the original spice JFET model.
Enhancements over the original model:
- Alan Gillespie's modified diode model
- Parallel multiplier
- Instance temperature as difference for circuit temperature
8.2 JFET2 - Junction Field Effect Transistor (PS model)
Ver: N/A
Class: J
Level: 2
Dir: devices/jfet2
Status:
This is the Parker Skellern model for MESFETs.
Web Site: http://www.elec.mq.edu.au/cnerf/psmodel.htm
Enhancements over the original model:
- Parallel multiplier
- Instance temperature as difference for circuit temperature
9. HFET Devices
Added code from macspice3f4 HFET1&2 and MESA model
Original note:
Added device calls for Mesfet models and HFET models
provided by Trond Ytterdal as of Nov 98
9.1 HFET1 - Heterostructure Field Effect Transistor Level 1
Ver: N/A
Class: Z
Level: 5
Dir: devices/hfet1
Status:
This is the Heterostructure Field Effect Transistor model from:
K. Lee, M. Shur, T. A. Fjeldly and T. Ytterdal
"Semiconductor Device Modeling in VLSI",
1993, Prentice Hall, New Jersey
Enhancements over the original model:
- Parallel multiplier
- Instance temperature as difference for circuit temperature
- Added pole-zero analysis
9.2 HFET2 - Heterostructure Field Effect Transistor Level 2
Ver: N/A
Class: Z
Level: 6
Dir: devices/hfet2
Status:
Simplified version of hfet1
Enhancements over the original model:
- Parallel multiplier
- Instance temperature as difference for circuit temperature
- Added pole-zero analysis
10. MES devices
10.1 MES - MESFET model
Ver: N/A
Class: Z
Level: 1
Dir: devices/mes
Status:
This is the original spice3 MESFET model (Statz).
Enhancements over the original model:
- Parallel multiplier
- Alan Gillespie junction diodes implementation
Added code from macspice3f4 HFET1&2 and MESA model
Original note:
Added device calls for Mesfet models and HFET models
provided by Trond Ytterdal as of Nov 98
10.2 MESA - MESFET model (MacSpice3f4)
Ver: N/A
Class: Z
Level: 2,3,4
Dir: devices/mesa
Status:
This is a multilevel model. It contains code for mesa levels
2,3 and 4
Enhancements over the original model:
- Parallel multiplier
- Instance temperature as difference from circuit temperature
- Added pole-zero analysis
11. MOS devices
11.1 MOS1 - Level 1 MOS model
Ver: N/A
Class: M
Level: 1
Dir: devices/mos1
Status:
This is the so-called Schichman-Hodges model.
Enhancements over the original model:
- Parallel multiplier
- Temperature difference from circuit temperature
11.2 MOS2 - Level 2 MOS model
Ver: N/A
Class: M
Level: 2
Dir: devices/mos2
Status:
This is the so-called Grove-Frohman model.
Enhancements over the original model:
- Parallel multiplier
- Temperature difference from circuit temperature
11.3 MOS3 - Level 3 MOS model
Ver: N/A
Class: M
Level: 3
Dir: devices/mos3
Status:
Enhancements over the original model:
- Parallel multiplier
- Temperature difference from circuit temperature
11.4 MOS6 - Level 6 MOS model
Ver: N/A
Class: M
Level: 6
Dir: devices/mos6
Status:
Enhancements over the original model:
- Parallel multiplier
- Temperature difference from circuit temperature
11.5 MOS9 - Level 9 MOS model
Ver: N/A
Class: M
Level: 9
Dir: devices/mos9
Status:
This is a slightly modified Level 3 MOSFET model.
(Whatever the implementer have had in mind.)
Not to confuse with Philips level 9.
Enhancements over the original model:
- Temperature difference from circuit temperature
11.6 BSIM1 - BSIM model level 1
Ver: N/A
Class: M
Level: 4
Dir: devices/bsim1
Status:
Enhancements over the original model:
- Parallel multiplier
- Noise analysis
BUGS:
Distortion analysis probably does not
work with "parallel" devices. Equations
are too intricate to deal with. Any one
has ideas on the subject ?
11.7 BSIM2 - BSIM model level 2
Ver: N/A
Class: M
Level: 5
Dir: devices/bsim2
Status:
Enhancements over the original model:
- Parallel multiplier
- Noise analysis
11.8 BSIM3v0 - BSIM model level 3
Ver: 3.0
Class: M
Level: 8 & 49, version = 3.0
Dir: devices/bsim3v0
Status: TO BE TESTED AND IMPROVED
11.9 BSIM3v1 - BSIM model level 3
Ver: 3.1
Class: M
Level: 8 & 49, version = 3.1
Dir: devices/bsim3v1
Status: TO BE TESTED AND IMPROVED
This is the BSIM3v3.1 model modified by Serban Popescu.
This is level 49 model. It is an implementation that supports
"HDIF" and "M" parameters.
11.10 BSIM3 - BSIM model level 3
Ver: 3.2.4
Class: M
Level: 8 & 49, version = 3.2.2, 3.2.3, 3.2.4
Dir: devices/bsim3v32 (level 3.2.4)
Status: o.k.
This is another BSIM3 model from Berkeley Device Group.
You can find some test netlists with results for this model
on its web site.
Web site: http://www-device.eecs.berkeley.edu/~bsim3
Enhancements over the original model:
- Parallel Multiplier
- delvto, mulu0 instance parameter
- ACM Area Calculation Method
- Multirevision code (supports all 3v3.2 minor revisions)
- NodesetFix
11.11 BSIM3 - BSIM model level 3
Ver: 3.3.0
Class: M
Level: 8 & 49, version = 3.3.0
Dir: devices/bsim3 (level 3.3.0)
Status: o.k.
This is the actual BSIM3 model from Berkeley Device Group.
You can find some test netlists with results for this model
on its web site.
Web site: http://www-device.eecs.berkeley.edu/~bsim3
Enhancements over the original model:
- Parallel Multiplier
- ACM Area Calculation Method
- Multirevision code (supports all 3v3.2 minor revisions)
- NodesetFix
- Support for Multi-core processors using OpenMP
11.12 BSIM4 - BSIM model level 4
Ver: 4.2.0 - 4.6.5
Class: M
Level: 14 & 54, version = 4.5, 4.6, 4.7, 4.8
Dir: devices/bsim4 (level 4.8.0)
Status: o.k.
This is the actual BSIM4 model from Berkeley Device Group.
Test are available on its web site.
Web site: http://www-device.eecs.berkeley.edu/~bsim3/bsim4.html
Enhancements over the original model:
- Parallel Multiplier
- NodesetFix
- Support for Multi-core processors using OpenMP
11.13 HiSIM2 - Hiroshima-university STARC IGFET Model
Ver: 2.8.0
Class: M
Level: 68
Dir: devices/hisim2
Status: TO BE TESTED.
This is the HiSIM2 model available from Hiroshima University
(Ultra-Small Device Engineering Laboratory)
Web site: http://home.hiroshima-u.ac.jp/usdl/HiSIM.html
Enhancements over the original model:
- Support for Multi-core processors using OpenMP
11.14 HiSIM_HV - Hiroshima-University STARC IGFET High Voltage Model
Ver: 1.2.4 and 2.2
Class: M
Level: 73
Dir: devices/hisimhv
Status: TO BE TESTED.
This is the HiSIM_HV model version 1 and 2 available from
Hiroshima University (Ultra-Small Device Engineering Laboratory)
Web site: http://home.hiroshima-u.ac.jp/usdl/HiSIM.html
11.15 VDMOS - Simple PowerMOS model
Ver: 1
Class: M
Level: -
Dir: devices/vdmos
Status: o.k.
This is a simplified Power MOS model, derived from MOS1 and
diode, similar to LTSPICE and SuperSpice VDMOS
Enhancements over the original model:
- Self heating with temp nodes junction and case
- Weak inversion
- Quasi-saturation
12. SOI devices
12.1 BSIM3SOI_FD - SOI model (fully depleted devices)
Ver: 2.1
Class: M
Level: 55
Dir: devices/bsim3soi_fd
Status: TO BE TESTED.
FD model has been integrated.
There is a bsim3soifd directory under the test
hierarchy. Test circuits come from the bsim3soi
Web site at: http://www-device.eecs.berkeley.edu/~bsimsoi
12.2 BSIM3SOI_DD - SOI Model (dynamic depletion model)
Ver: 2.1
Class: M
Level: 56
Dir: devices/bsim3soi_dd
Status: TO BE TESTED.
There is a bsim3soidd directory under the
test hierarchy. Test circuits come from bsim3soi
Web site at: http://www-device.eecs.berkeley.edu/~bsimsoi
12.3 BSIM3SOI_PD - SOI model (partially depleted devices)
Ver: 2.2.1
Class: M
Level: 57
Dir: devices/bsim3soi_pd
Status: TO BE TESTED.
PD model has been integrated. There is a bsim3soipd directory
under the test hierarchy. Test circuits come from the bsim3soi
Web site at: http://www-device.eecs.berkeley.edu/~bsimsoi
12.4 BSIMSOI - Berkeley SOI model (partially/full depleted devices)
Ver: 4.3.1
Class: M
Level: 10 & 58
Dir: devices/bsim3soi
Status: o.k.
This is the actual version from Berkeley. This version is
backward compatible with its previous versions BSIMSOI3.x.
Usable for partially/full depleted devices.
Web site at: https://bsim.berkeley.edu/models/bsimsoi/
Enhancements over the original model:
- Parallel Multiplier
- Support for Multi-core processors using OpenMP
12.5 SOI3 - STAG SOI3 Model
Ver: 2.6
Class: M
Level: 60
Dir: devices/soi3
Status: OBSOLETE
13. Verilog-A models
ngspice inherits the OSDI interface for compiled Verilog-A models
OpenVAF from https://openvaf.semimod.de/ is required to compile
LRM2.x-conforming Verilog-A models into shared libraries which
may be loaded into ngspice dynamically at run-time.
The following models have been tested, example netlists are available:
13.1 BSIMBULK 107
13.2 BSIM-CMG
13.3 HICUM L0
13.4 ASM-HEMT
13.5 VBIC
13.6 MEXTRAM 504/505
13.7 PSP 103.8
13.8 r2_cmc
More models are available at https://github.com/dwarning/VA-Models,
user compiled models are possible as well (See ngspice manual, chapter 13).
14. XSpice code models
more than 100 models are available, please see ngspice manual chapt. 12
15. Digital Building Blocks (U instances)
U instances are digital primitives which may be used (in proper combination) to
model digital devices, e.g. from the 74xx or 40xx families. ngspice maps them
onto XSPICE models, which allows a fast event based simulation. Please see the
ngspice manual, chapter 14.
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