46 lines
1.5 KiB
Plaintext
46 lines
1.5 KiB
Plaintext
* simple voltage regulator, example for traditional feedback loop analysis using L and C
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Mout out pgate vdd vdd p1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p m=100
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R1 out fb 33.3K
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R2 fb vss 66.7K
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Mp1 mir mir vdd vdd p1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p m=2
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Mp2 pgate mir vdd vdd p1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p m=2
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M1 pgate set tail vss n1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p m=10
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M2 mir fbinj tail vss n1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p m=10
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Cc pgate vdd 10p
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Mb1 tail bn vss vss n1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p m=4
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Mb0 bn bn vss vss n1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p m=4
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Ib vss bn 1u
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* breaking the loop with huge inductor
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Lloop fb fbinj 100e6
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* injecting AC trough huge capacitor
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Cinj inj fbinj 100e6
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Vinj inj 0 DC 0 AC 1
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* load replication for node 'fb' (approximate)
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M2rep mirrep fb tailrep vss n1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p m=10
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Mp1rep mirrep mirrep vdd vdd p1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p m=2
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Mb1rep tailrep bn vss vss n1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p m=2
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Vset set vss DC 1.2
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Vvdd vdd vss DC 3.3
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Vvss vss 0 DC 0
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Cload out vss 100p
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Iload out vss DC 10e-3 PWL 1n 10e-3 2n 1e-3
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.model n1 nmos level=49 version=3.3.0 tox=3.5n nch=2.4e17 nsub=5e16 vth0=0.6
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.model p1 pmos level=49 version=3.3.0 tox=3.5n nch=2.5e17 nsub=5e16 vth0=-0.7
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.option gmin=1e-14 reltol=1e-5 abstol=1e-14
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.ac dec 10 1 10e9
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.control
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ac dec 10 1 10e9
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plot db(fb)
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.endc
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