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Giles Atkinson
35968d1da6
source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking.
35 lines
608 B
Verilog
35 lines
608 B
Verilog
`timescale 1us/100ns
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//`include "constants.vams"
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`define M_TWO_PI 6.28318530717958647652
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module pwm(out);
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output reg out;
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parameter Cycles = 1000, Samples = 1000;
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integer i, j, width;
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real sine;
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initial begin
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i = 0;
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j = 0;
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width = Cycles / 2;
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out = 0;
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end
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always begin
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#1;
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++i;
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if (i == width)
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out = 0;
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if (i == Cycles) begin
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i = 0;
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++j;
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if (j == Samples)
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j = 0;
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sine = $sin(j * `M_TWO_PI / Samples);
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width = $rtoi(Samples * (1.0 + sine) / 2.0);
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out = (width == 0) ? 0 : 1;
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end
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end
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endmodule // pwm
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