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Giles Atkinson
1244f4dc1f
source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking.
27 lines
567 B
Verilog
27 lines
567 B
Verilog
// Very simple logic for a 555 timer simulation
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`timescale 1us/100ns
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module VL555(Trigger, Threshold, Reset, Q, Qbar);
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input wire Trigger, Threshold, Reset; // Reset is active low.
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output reg Q;
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output wire Qbar;
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wire ireset, go;
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assign Qbar = !Q;
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// The datasheet implies that Trigger overrides Threshold.
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assign go = Trigger & Reset;
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assign ireset = (Threshold & !Trigger) | !Reset;
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initial begin
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Q = 0;
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end
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always @(posedge(go), posedge(ireset)) begin
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Q = go;
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end
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endmodule
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