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VBIC: lean and mean code revision

This commit is contained in:
dwarning 2025-01-30 14:47:34 +01:00 committed by dwarning
parent 0b61e6b38e
commit fdecb84ff9
6 changed files with 99 additions and 1336 deletions
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13
src/spicelib/devices/vbic/vbic.c
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@ -36,14 +36,16 @@ IFparm VBICpTable[] = { /* parameters */
OPU("baseBPnode",VBIC_QUEST_BASEBPNODE,IF_INTEGER, "Internal base node"),
OPU("emitEInode",VBIC_QUEST_EMITEINODE,IF_INTEGER, "Internal emitter node"),
OPU("subsSInode",VBIC_QUEST_SUBSSINODE,IF_INTEGER, "Internal substrate node"),
OPU("xf1node", VBIC_QUEST_XF1NODE, IF_INTEGER, "Internal phase node xf1"),
OPU("xf2node", VBIC_QUEST_XF2NODE, IF_INTEGER, "Internal phase node xf2"),
OP("vbe", VBIC_QUEST_VBE, IF_REAL, "B-E voltage"),
OP("vbc", VBIC_QUEST_VBC, IF_REAL, "B-C voltage"),
OP("ic", VBIC_QUEST_CC, IF_REAL, "Collector current"),
OP("ib", VBIC_QUEST_CB, IF_REAL, "Base current"),
OP("ie", VBIC_QUEST_CE, IF_REAL, "Emitter current"),
OP("is", VBIC_QUEST_CS, IF_REAL, "Substrate current"),
OP("p", VBIC_QUEST_POWER,IF_REAL, "Power dissipation"),
OPR("power",VBIC_QUEST_POWER,IF_REAL, "Power dissipation"),
OP("beta", VBIC_QUEST_BETA, IF_REAL, "CE current gain DC"),
OPR("betad",VBIC_QUEST_BETA, IF_REAL, "CE current gain DC"),
OP("gm", VBIC_QUEST_GM, IF_REAL, "Small signal transconductance dIc/dVbe"),
OP("go", VBIC_QUEST_GO, IF_REAL, "Small signal output conductance dIc/dVbc"),
OP("gpi", VBIC_QUEST_GPI, IF_REAL, "Small signal input conductance dIb/dVbe"),
@ -55,15 +57,8 @@ IFparm VBICpTable[] = { /* parameters */
OP("cbcx", VBIC_QUEST_CBCX, IF_REAL, "External Base to collector capacitance"),
OP("cbep", VBIC_QUEST_CBEP, IF_REAL, "Parasitic Base to emitter capacitance"),
OP("cbcp", VBIC_QUEST_CBCP, IF_REAL, "Parasitic Base to collector capacitance"),
OP("p", VBIC_QUEST_POWER,IF_REAL, "Power dissipation"),
OPU("geqcb",VBIC_QUEST_GEQCB,IF_REAL, "Internal C-B-base cap. equiv. cond."),
OPU("geqbx",VBIC_QUEST_GEQBX,IF_REAL, "External C-B-base cap. equiv. cond."),
OPU("qbe", VBIC_QUEST_QBE, IF_REAL, "Charge storage B-E junction"),
OPU("cqbe", VBIC_QUEST_CQBE, IF_REAL, "Cap. due to charge storage in B-E jct."),
OPU("qbc", VBIC_QUEST_QBC, IF_REAL, "Charge storage B-C junction"),
OPU("cqbc", VBIC_QUEST_CQBC, IF_REAL, "Cap. due to charge storage in B-C jct."),
OPU("qbx", VBIC_QUEST_QBX, IF_REAL, "Charge storage B-X junction"),
OPU("cqbx", VBIC_QUEST_CQBX, IF_REAL, "Cap. due to charge storage in B-X jct.")
};
IFparm VBICmPTable[] = { /* model parameters */

1
src/spicelib/devices/vbic/vbicacld.c
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@ -251,7 +251,6 @@ c Stamp element: Rs
Ibe_Vrth = here->VBICibe_Vrth;
Ibex_Vrth = here->VBICibex_Vrth;
Iciei_Vrth = here->VBICiciei_Vrth;
Ibc_Vrth = here->VBICibc_Vrth;
Ibep_Vrth = here->VBICibep_Vrth;
Ircx_Vrth = here->VBICircx_Vrth;

31
src/spicelib/devices/vbic/vbicask.c
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@ -22,9 +22,11 @@ Spice3 Implementation: 2003 Dietmar Warning DAnalyse GmbH
int
VBICask(CKTcircuit *ckt, GENinstance *instPtr, int which, IFvalue *value, IFvalue *select)
{
IFvalue IC, IB, IE, IS;
NG_IGNORE(select);
VBICinstance *here = (VBICinstance*)instPtr;
IFvalue IC, IB;
switch(which) {
case VBIC_AREA:
value->rValue = here->VBICarea;
@ -76,6 +78,7 @@ VBICask(CKTcircuit *ckt, GENinstance *instPtr, int which, IFvalue *value, IFvalu
return(OK);
case VBIC_QUEST_CC:
value->rValue = *(ckt->CKTstate0 + here->VBICiciei) -
*(ckt->CKTstate0 + here->VBICiccp) -
*(ckt->CKTstate0 + here->VBICibc);
value->rValue *= VBICmodPtr(here)->VBICtype;
return(OK);
@ -99,26 +102,16 @@ VBICask(CKTcircuit *ckt, GENinstance *instPtr, int which, IFvalue *value, IFvalu
value->rValue *= VBICmodPtr(here)->VBICtype;
return(OK);
case VBIC_QUEST_POWER:
value->rValue = fabs(here->VBICpower);
return(OK);
case VBIC_QUEST_BETA:
VBICask(ckt, instPtr, VBIC_QUEST_CC, &IC, select);
VBICask(ckt, instPtr, VBIC_QUEST_CB, &IB, select);
VBICask(ckt, instPtr, VBIC_QUEST_CE, &IE, select);
VBICask(ckt, instPtr, VBIC_QUEST_CS, &IS, select);
if (!here->VBIC_excessPhase)
value->rValue = fabs(*(ckt->CKTstate0 + here->VBICibe) * *(ckt->CKTstate0 + here->VBICvbei)) +
fabs(*(ckt->CKTstate0 + here->VBICibc) * *(ckt->CKTstate0 + here->VBICvbci)) +
fabs(*(ckt->CKTstate0 + here->VBICiciei))
* fabs(*(ckt->CKTstate0 + here->VBICvbei) - *(ckt->CKTstate0 + here->VBICvbci)) +
fabs(*(ckt->CKTstate0 + here->VBICibex) * *(ckt->CKTstate0 + here->VBICvbex)) +
fabs(*(ckt->CKTstate0 + here->VBICibep) * *(ckt->CKTstate0 + here->VBICvbep)) +
fabs(*(ckt->CKTstate0 + here->VBICibcp) * *(ckt->CKTstate0 + here->VBICvbcp)) +
fabs(*(ckt->CKTstate0 + here->VBICiccp))
* fabs(*(ckt->CKTstate0 + here->VBICvbep) - *(ckt->CKTstate0 + here->VBICvbcp)) +
fabs(IC.rValue * IC.rValue * here->VBICtextCollResist) +
fabs(IC.rValue * *(ckt->CKTstate0 + here->VBICvrci)) +
fabs(IB.rValue * IB.rValue * here->VBICtextBaseResist) +
fabs(IB.rValue * *(ckt->CKTstate0 + here->VBICvrbi)) +
fabs(IE.rValue * IE.rValue * here->VBICtemitterResist) +
fabs(IS.rValue * *(ckt->CKTstate0 + here->VBICvrbp));
if (IB.rValue != 0.0) {
value->rValue = IC.rValue/IB.rValue;
} else {
value->rValue = 0.0;
}
return(OK);
case VBIC_QUEST_GM:
value->rValue = *(ckt->CKTstate0 + here->VBICiciei_Vbei);

25
src/spicelib/devices/vbic/vbicdefs.h
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@ -312,6 +312,8 @@ typedef struct sVBICinstance {
double VBICith_Vre;
double VBICith_Vrs;
double VBICpower;
int VBIC_selfheat; /* self-heating enabled */
int VBIC_excessPhase; /* excess phase enabled */
@ -933,8 +935,7 @@ enum {
/* device questions */
enum {
VBIC_QUEST_FT = 221,
VBIC_QUEST_COLLNODE,
VBIC_QUEST_COLLNODE = 221,
VBIC_QUEST_BASENODE,
VBIC_QUEST_EMITNODE,
VBIC_QUEST_SUBSNODE,
@ -945,39 +946,27 @@ enum {
VBIC_QUEST_BASEBPNODE,
VBIC_QUEST_EMITEINODE,
VBIC_QUEST_SUBSSINODE,
VBIC_QUEST_XF1NODE,
VBIC_QUEST_XF2NODE,
VBIC_QUEST_VBE,
VBIC_QUEST_VBC,
VBIC_QUEST_CC,
VBIC_QUEST_CB,
VBIC_QUEST_CE,
VBIC_QUEST_CS,
VBIC_QUEST_POWER,
VBIC_QUEST_BETA,
VBIC_QUEST_GM,
VBIC_QUEST_GO,
VBIC_QUEST_GPI,
VBIC_QUEST_GMU,
VBIC_QUEST_GX,
VBIC_QUEST_QBE,
VBIC_QUEST_CQBE,
VBIC_QUEST_QBC,
VBIC_QUEST_CQBC,
VBIC_QUEST_QBX,
VBIC_QUEST_CQBX,
VBIC_QUEST_QBCP,
VBIC_QUEST_CQBCP,
VBIC_QUEST_CEXBC,
VBIC_QUEST_GEQCB,
VBIC_QUEST_GCSUB,
VBIC_QUEST_GDSUB,
VBIC_QUEST_GEQBX,
VBIC_QUEST_CBE,
VBIC_QUEST_CBEX,
VBIC_QUEST_CBC,
VBIC_QUEST_CBCX,
VBIC_QUEST_CBEP,
VBIC_QUEST_CBCP,
VBIC_QUEST_POWER,
VBIC_QUEST_QBE,
VBIC_QUEST_QBC,
};
/* model questions */

1301
src/spicelib/devices/vbic/vbicload.c
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File diff suppressed because it is too large Load Diff

2
src/spicelib/devices/vbic/vbicpzld.c
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@ -66,6 +66,7 @@ VBICpzLoad(GENmodel *inModel, CKTcircuit *ckt, SPcomplex *s)
Ibex_Vbex = *(ckt->CKTstate0 + here->VBICibex_Vbex);
Iciei_Vbei = *(ckt->CKTstate0 + here->VBICiciei_Vbei);
Iciei_Vbci = *(ckt->CKTstate0 + here->VBICiciei_Vbci);
Iciei_Vrth = *(ckt->CKTstate0 + here->VBICiciei_Vrth);
Iciei_Vxf2 = *(ckt->CKTstate0 + here->VBICiciei_Vxf2);
Ibc_Vbci = *(ckt->CKTstate0 + here->VBICibc_Vbci);
Ibc_Vbei = *(ckt->CKTstate0 + here->VBICibc_Vbei);
@ -250,7 +251,6 @@ c Stamp element: Rs
Ibe_Vrth = here->VBICibe_Vrth;
Ibex_Vrth = here->VBICibex_Vrth;
Iciei_Vrth = here->VBICiciei_Vrth;
Ibc_Vrth = here->VBICibc_Vrth;
Ibep_Vrth = here->VBICibep_Vrth;
Ircx_Vrth = here->VBICircx_Vrth;