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Fix ordering of parameter definition and use. 

Icarus Verilog no longer accepts use-before-definition.
Also slightly expand the README for Icarus Verilog examples.
This commit is contained in:
Giles Atkinson 2025-01-19 11:42:45 +00:00 committed by Holger Vogt
parent 0c2a287d3c
commit fd3827af40
2 changed files with 6 additions and 2 deletions
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4
examples/xspice/icarus_verilog/README.txt
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@ -5,6 +5,10 @@ so that its simulation engine is available as a dynamic library.
The Verilog source code and included parts of the circuit definitions The Verilog source code and included parts of the circuit definitions
can be found in the adjacent "verilator" directory. can be found in the adjacent "verilator" directory.
The circuits and steps below are intended to be used from the directory
containing this file, certainly ouput files from iverilog should be in
the current directory when simulating.
The example circuits are: The example circuits are:
555.cir: The probably familiar NE555 oscillator provides a minimal example 555.cir: The probably familiar NE555 oscillator provides a minimal example

4
examples/xspice/verilator/adc.v
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@ -3,12 +3,12 @@
`timescale 100ns/100ns `timescale 100ns/100ns
module adc(Clk, Comp, Start, Sample, Done, Result); module adc(Clk, Comp, Start, Sample, Done, Result);
parameter Bits=6;
input wire Clk, Comp, Start; input wire Clk, Comp, Start;
output reg Sample, Done; output reg Sample, Done;
output reg [Bits - 1 : 0] Result; output reg [Bits - 1 : 0] Result;
parameter Bits=6;
reg [Bits - 1 : 0] SR; reg [Bits - 1 : 0] SR;
reg Running; reg Running;