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Obtain memory and simulation time 

Add rusage information command
This commit is contained in:
Holger Vogt 2022-01-03 21:57:38 +01:00
parent fb92ac8f16
commit eb4b141f4b
7 changed files with 7 additions and 0 deletions
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1
examples/memristor/memristor_x.sp
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@ -78,6 +78,7 @@ plot res vs time res1 vs tran1.time res2 vs tran2.time title 'Memristor with th
plot res vs v(1) res1 vs tran1.v(1) res2 vs tran2.v(1) retraceplot title 'Memristor with threshold: resistance' plot res vs v(1) res1 vs tran1.v(1) res2 vs tran2.v(1) retraceplot title 'Memristor with threshold: resistance'
* current through resistor for all plots versus voltage * current through resistor for all plots versus voltage
plot i(v1) vs v(1) tran1.i(v1) vs tran1.v(1) tran2.i(v1) vs tran2.v(1) retraceplot title 'Memristor with threshold: external current loops' plot i(v1) vs v(1) tran1.i(v1) vs tran1.v(1) tran2.i(v1) vs tran2.v(1) retraceplot title 'Memristor with threshold: external current loops'
rusage
.endc .endc
.end .end

1
examples/xspice/d_lut/mult4bit.spi
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@ -103,6 +103,7 @@ Xmult4 p7 p6 p5 p4 p3 p2 p1 p0 a3 a2 a1 a0 b3 b2 b1 b0 mult4bit
.control .control
tran 50us 12825us 25us tran 50us 12825us 25us
rusage
linearize linearize
let aa = (((v(a3))*2 + v(a2))*2 + v(a1))*2 + v(a0) let aa = (((v(a3))*2 + v(a2))*2 + v(a1))*2 + v(a0)

1
examples/xspice/d_source/PWMexample.net
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@ -17,6 +17,7 @@ C1 0 1 10n
.control .control
save 33 44 1 save 33 44 1
tran 1us 50m tran 1us 50m
rusage
wrdata $inputdir/fil2.dat V(33) v(44) V(1) wrdata $inputdir/fil2.dat V(33) v(44) V(1)
plot v(44) V(1) xlimit 22.9m 23m plot v(44) V(1) xlimit 22.9m 23m
.endc .endc

1
examples/xspice/delay/analog-delay1.cir
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@ -39,6 +39,7 @@ Vc5 cntrl5 0 0
.control .control
tran 1u 10m tran 1u 10m
rusage
set xbrushwidth=2 set xbrushwidth=2
plot v(in1) V(out1) title 'Const delay' plot v(in1) V(out1) title 'Const delay'
plot v(in2) V(out2) title 'Variable delay' plot v(in2) V(out2) title 'Variable delay'

1
examples/xspice/delta-sigma/delta-sigma-1.cir
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@ -95,6 +95,7 @@ abridge22 [dclk xsinc.ddivndel1 xsinc.ddivndel2 dv] [acclk acset acres acin] dac
.control .control
save inp inm adaclout adaccout ; save memory space save inp inm adaclout adaccout ; save memory space
tran 0.1u $&simtime tran 0.1u $&simtime
rusage
* analog out, scaled 'manually'; sinc filter counter; analog differential in * analog out, scaled 'manually'; sinc filter counter; analog differential in
plot 4.1*(adaclout-0.486) adaccout v(inp)-v(inm) ylimit -0.6 0.6 plot 4.1*(adaclout-0.486) adaccout v(inp)-v(inm) ylimit -0.6 0.6
* modulator dig out * modulator dig out

1
examples/xspice/filesource/simple-filesource.cir
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@ -22,6 +22,7 @@ Rload2 N_IN2 0 1k
option NOINIT ACCT option NOINIT ACCT
tran 1us 100us tran 1us 100us
rusage
display display
plot allv plot allv
.endc .endc

1
examples/xspice/state/state-machine.cir
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@ -29,6 +29,7 @@ a5 cntl clk var_clock
.control .control
tran 1us 10ms tran 1us 10ms
rusage
write spifsim.raw write spifsim.raw
plot cntl out_msb+2 out_lsb+8 plot cntl out_msb+2 out_lsb+8
eprvcd n_one clk n_zero msb lsb > spifsim.vcd eprvcd n_one clk n_zero msb lsb > spifsim.vcd