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cktop.c, #3/14, combine two `if' bodies

This commit is contained in:
rlar 2016-07-24 16:12:28 +02:00
parent ec1e1114e8
commit eb1c8e92bc
1 changed files with 2 additions and 2 deletions
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4
src/spicelib/analysis/cktop.c
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@ -430,6 +430,7 @@ gillespie_src (CKTcircuit * ckt, long int firstmode,
/* If we've got convergence, then try stepping up the sources */ /* If we've got convergence, then try stepping up the sources */
if (converged == 0) { if (converged == 0) {
for (i = 0, n = ckt->CKTnodes; n; n = n->next) for (i = 0, n = ckt->CKTnodes; n; n = n->next)
OldRhsOld[i++] = ckt->CKTrhsOld[n->number]; OldRhsOld[i++] = ckt->CKTrhsOld[n->number];
@ -439,10 +440,8 @@ gillespie_src (CKTcircuit * ckt, long int firstmode,
SPfrontEnd->IFerrorf (ERR_INFO, SPfrontEnd->IFerrorf (ERR_INFO,
"One successful source step"); "One successful source step");
ckt->CKTsrcFact = ConvFact + raise; ckt->CKTsrcFact = ConvFact + raise;
}
if (converged == 0)
do { do {
fprintf (stderr, fprintf (stderr,
"Supplies reduced to %8.4f%% ", ckt->CKTsrcFact * 100); "Supplies reduced to %8.4f%% ", ckt->CKTsrcFact * 100);
@ -504,6 +503,7 @@ gillespie_src (CKTcircuit * ckt, long int firstmode,
ckt->CKTsrcFact = 1; ckt->CKTsrcFact = 1;
} while ((raise >= 1e-7) && (ConvFact < 1)); } while ((raise >= 1e-7) && (ConvFact < 1));
}
FREE (OldRhsOld); FREE (OldRhsOld);
FREE (OldCKTstate0); FREE (OldCKTstate0);