instructions for simd

src/spicelib/devices/bsim3v32/INSTALL

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+BSIM3V32SIMD is to be used with ngspice version 32, or the current development branch as for July 2020.
+It might work with other versions as well.
+For installing BSIM3V3SIMD, the ngspice source code is required.
+
+Extraction:
+- go to ngspice source code tree at <ngspice>/src/spicelib/devices
+- extract BSIM3V32SIMD.tar.gz
+- this will replace and add files in the directory bsim3v32
+
+Compilation on a target computer supporting AVX2:
+- go to the base of ngspice source tree
+- run automake (or ./autogen.sh)
+- mkdir buildsimd
+- cd buildsimd
+- ../configure CFLAGS="-O3 -march=native" (add your configure flags as required)
+- make (the compiler must be a recent gcc or clang, other compilers not tested).
+- make install (or use directly the <ngspice>/buildsimd/src/ngspice binary)
+
+Usage:
+The new optimized model will be used automatically if you have any BSIM3V32 devices in your simulated circuit.
+For other devices models, there will be no speed-up at all.
+
+Notes:
+Compiling for architectures other than x86_64 with AVX2 was not tested.
+It should be possible if the target architecture supports vector processing for double precision floating point numbers with vector length of 4 or more.
+In file b3v32ldsimd.c, set USEX86INTRINSICS to 0 and modify definition of functions vec4_MAX, vec4_exp, vec4_log, vec4_sqrt, vec4_blend, vec4_fabs with an adequate implementation for your achitecture.
+
+Compiling for vector length of 8 was not tested.
+It should be possible if the target architecture supports it.
+Change NSIMD value from 4 to 8 in bsim3v32def.h.
+In file b3v32ldsimd.c, provides new functions vec8_* for all functions vec4_*. 
+
+Anamosic Ballenegger Design, July 2020
+www.anamosic.com

src/spicelib/devices/bsim3v32/README

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+/**********
+ * BSIM3V32 MOSFET device model form the UC Berkeley BSIM Research Group
+ * Copyright 2001 Regents of the University of California. All rights reserved.
+ **********/
+ 
+/**********
+ * Modified 2020 by Florian Ballenegger, Anamosic Ballenegger Design
+ * Copyright 2020 Florian Ballenegger, Anamosic Ballenegger Design, Switzerland
+ * Modified code is distributed under the same license terms as the original,
+ * see file "B3TERMS_OF_USE".
+ **********/
+
+BSIM3V32SIMD is a modified version of the widely used BSIM3V32 model, using SIMD instructions to evaluate several devices in parallel and to speed-up the simulation, with almost the same accuracy (the only loss of accuracy comes from the use of slightly less accurate exp and log functions).
+
+Contrary to parallel device evaluation available with OpenMP multiprocessing, BSIM3V32SIMD does load only 1 CPU core per simulation while achieving about 2x speed-up.
+This means that this optimization is also usefull when a batch of multiple simulations is desired for statistical analysis.
+
+BSIM3V32SIMD can be combined with OpenMP multiprocessing to achieve about 3x speed-up for an single simulation run.
+
+The actual acceleration will depend on the simulated circuit and will the most for medium-sized circuit consisting of mainly MOS transistors in the number of one hundred to ten thousands, as it is usual in the design of integrated circuit blocks. If simulating greater circuit, the matrix solving time will start to dominates and overall the optimization will have less effect.
+
+
+New Files:
+README
+INSTALL
+b3v32ldsel.c
+b3v32ldseq.c
+b3v32ldsimd.c
+b3v32ldseq_simd4.c
+b3v32ldseq_simd4_omp.c
+vec4_exp.c
+vec4_log.c
+
+Modified Files:
+Makefile.am
+bsim3v32def.h
+bsim3v32ext.h
+bsim3v32init.c
+b3v32set.c
+b3v32ld.c (minor modifications, can use original as well)
+
+Anamosic Ballenegger Design, July 2020
+www.anamosic.com