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3rd and 4th node have to be the same for VDMOS

This commit is contained in:
Holger Vogt 2018-07-22 00:31:29 +02:00
parent d61fa145c1
commit de644fe3ca
2 changed files with 2 additions and 2 deletions
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2
examples/vdmos/vdmos-out_ir.cir
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VDMOS output VDMOS output
m1 d g s b IRFZ48Z m1 d g s s IRFZ48Z
.model IRFZ48Z VDMOS ( Rg = 1.77 Vto=4 Rd=1.85m Rs=0.0m Rb=3.75m Kp=25 Cgdmax=2.1n Cgdmin=0.05n Cgs=1.8n Cjo=0.55n Is=2.5p tt=20n mfg=International_Rectifier Vds=55 Ron=8.6m Qg=43n) .model IRFZ48Z VDMOS ( Rg = 1.77 Vto=4 Rd=1.85m Rs=0.0m Rb=3.75m Kp=25 Cgdmax=2.1n Cgdmin=0.05n Cgs=1.8n Cjo=0.55n Is=2.5p tt=20n mfg=International_Rectifier Vds=55 Ron=8.6m Qg=43n)

2
examples/vdmos/vdmosp-out.cir
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VDMOS p channel output VDMOS p channel output
m1 d g s b p1 m1 d g s s p1
.model p1 vdmos pchan vto=-1.2 is=10n kp=2 bv=-12 rb=1k .model p1 vdmos pchan vto=-1.2 is=10n kp=2 bv=-12 rb=1k
*d1 d s dmod *d1 d s dmod
*.model dmod d is=10n rs=0.1 *.model dmod d is=10n rs=0.1