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bring current summation inline with rhs

This commit is contained in:
dwarning 2018-12-24 09:34:06 +01:00
parent d9247cc322
commit d2f9da64bc
1 changed files with 7 additions and 7 deletions
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14
src/spicelib/devices/vdmos/vdmosload.c
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@ -144,14 +144,14 @@ VDMOSload(GENmodel *inModel, CKTcircuit *ckt)
if (here->VDMOSmode >= 0) { if (here->VDMOSmode >= 0) {
cdhat = cdhat =
here->VDMOScd - here->VDMOScd
here->VDMOSgm * delvgs + + here->VDMOSgm * delvgs
here->VDMOSgds * delvds; + here->VDMOSgds * delvds;
} else { } else {
cdhat = cdhat =
here->VDMOScd - here->VDMOScd
here->VDMOSgm * delvgd + - here->VDMOSgm * delvgd
here->VDMOSgds * delvds; + here->VDMOSgds * delvds;
} }
#ifndef NOBYPASS #ifndef NOBYPASS
@ -507,7 +507,7 @@ bypass :
*(ckt->CKTrhs + here->VDMOSgNodePrime) -= *(ckt->CKTrhs + here->VDMOSgNodePrime) -=
(model->VDMOStype * (ceqgs + ceqgd)); (model->VDMOStype * (ceqgs + ceqgd));
*(ckt->CKTrhs + here->VDMOSdNodePrime) += *(ckt->CKTrhs + here->VDMOSdNodePrime) +=
(- cdreq + model->VDMOStype * ceqgd); (-cdreq + model->VDMOStype * ceqgd);
*(ckt->CKTrhs + here->VDMOSsNodePrime) += *(ckt->CKTrhs + here->VDMOSsNodePrime) +=
cdreq + model->VDMOStype * ceqgs; cdreq + model->VDMOStype * ceqgs;