b4v4getic.c, cleanup indentation
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@ -17,28 +17,27 @@
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int
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int
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BSIM4v4getic(
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BSIM4v4getic(
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GENmodel *inModel,
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GENmodel *inModel,
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CKTcircuit *ckt)
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CKTcircuit *ckt)
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{
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{
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BSIM4v4model *model = (BSIM4v4model*)inModel;
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BSIM4v4model *model = (BSIM4v4model*)inModel;
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BSIM4v4instance *here;
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BSIM4v4instance *here;
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for (; model ; model = model->BSIM4v4nextModel)
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for (; model ; model = model->BSIM4v4nextModel) {
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{ for (here = model->BSIM4v4instances; here; here = here->BSIM4v4nextInstance)
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for (here = model->BSIM4v4instances; here; here = here->BSIM4v4nextInstance) {
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{
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if (!here->BSIM4v4icVDSGiven) {
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if (!here->BSIM4v4icVDSGiven)
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here->BSIM4v4icVDS = *(ckt->CKTrhs + here->BSIM4v4dNode)
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{ here->BSIM4v4icVDS = *(ckt->CKTrhs + here->BSIM4v4dNode)
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- *(ckt->CKTrhs + here->BSIM4v4sNode);
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- *(ckt->CKTrhs + here->BSIM4v4sNode);
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}
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}
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if (!here->BSIM4v4icVGSGiven) {
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if (!here->BSIM4v4icVGSGiven)
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here->BSIM4v4icVGS = *(ckt->CKTrhs + here->BSIM4v4gNodeExt)
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{ here->BSIM4v4icVGS = *(ckt->CKTrhs + here->BSIM4v4gNodeExt)
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- *(ckt->CKTrhs + here->BSIM4v4sNode);
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- *(ckt->CKTrhs + here->BSIM4v4sNode);
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}
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}
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if(!here->BSIM4v4icVBSGiven) {
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if(!here->BSIM4v4icVBSGiven)
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here->BSIM4v4icVBS = *(ckt->CKTrhs + here->BSIM4v4bNode)
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{ here->BSIM4v4icVBS = *(ckt->CKTrhs + here->BSIM4v4bNode)
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- *(ckt->CKTrhs + here->BSIM4v4sNode);
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- *(ckt->CKTrhs + here->BSIM4v4sNode);
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}
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}
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}
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}
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}
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}
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return(OK);
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return(OK);
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}
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}
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