luke
/
ngspice
mirror of https://git.code.sf.net/p/ngspice/ngspice
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Rename test_osdi_libs to osdi_libs

This commit is contained in:
Holger Vogt 2022-12-19 10:44:59 +01:00
parent a1641d5a78
commit bb9469a03a
42 changed files with 36 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
examples/osdi/EKV2.6/ekv26_inverter.sp
View File

@ -28,7 +28,7 @@ c2 z vss 0.576f
.dc V1 0 'vcc' 'vcc/100' .dc V1 0 'vcc' 'vcc/100'
.control .control
pre_osdi test_osdi_libs/ekv26_mod.osdi pre_osdi osdi_libs/ekv26_mod.osdi
run run
*set nolegend *set nolegend
set xbrushwidth=3 set xbrushwidth=3

2
examples/osdi/EKV2.6/netlist_mod_nmos.sp
View File

@ -15,7 +15,7 @@ VB bb 0 0
N1 dd gg ss bb nch W=5e-6 L=0.5e-6 N1 dd gg ss bb nch W=5e-6 L=0.5e-6
.control .control
pre_osdi test_osdi_libs/ekv26_mod.osdi pre_osdi osdi_libs/ekv26_mod.osdi
set xbrushwidth=3 set xbrushwidth=3
* a DC sweep: drain, gate * a DC sweep: drain, gate
dc Vd 0 1.6 0.01 VG 0 1.6 0.2 dc Vd 0 1.6 0.01 VG 0 1.6 0.2

2
examples/osdi/EKV2.6/netlist_mod_pmos.sp
View File

@ -15,7 +15,7 @@ VB bb 0 0
N1 dd gg ss bb pch W=5e-6 L=5e-7 N1 dd gg ss bb pch W=5e-6 L=5e-7
.control .control
pre_osdi test_osdi_libs/ekv26_mod.osdi pre_osdi osdi_libs/ekv26_mod.osdi
set xbrushwidth=3 set xbrushwidth=3
* a DC sweep: drain, gate * a DC sweep: drain, gate
*op *op

0
examples/osdi/EKV2.6/test_osdi_libs/README → examples/osdi/EKV2.6/osdi_libs/README
View File

6
examples/osdi/README
View File

@ -13,7 +13,7 @@ Search for the module name, here:
The module name 'bsimbulk' will become the new model type in the .model statement The module name 'bsimbulk' will become the new model type in the .model statement
.model mname type ( pname1 = pval1 pname2 = pval2 ... ). .model mname type ( pname1 = pval1 pname2 = pval2 ... ).
Compile bsimbulk.va with OpenVAF to obtain bsimbulk.osdi Compile bsimbulk.va with OpenVAF to obtain bsimbulk.osdi
Put bsimbulk.osdi into directory bsimbulk/test_osdi_libs Put bsimbulk.osdi into directory bsimbulk/osdi_libs
Search for suitable model parameters Search for suitable model parameters
BSIMBULK107 distro does not contain any parameters BSIMBULK107 distro does not contain any parameters
BSIMBULK106 does contain a model parameter file model.l among the benchmark tests BSIMBULK106 does contain a model parameter file model.l among the benchmark tests
@ -41,7 +41,7 @@ NMN1 dd gg ss bb BSIMBULK_osdi_N W=500n L=90n
* the .control section * the .control section
.control .control
* load the model dynamically * load the model dynamically
pre_osdi test_osdi_libs/bsimbulk.osdi pre_osdi osdi_libs/bsimbulk.osdi
* the dc simulation * the dc simulation
dc Vg 0 1.5 0.01 Vb 0 -1.6 -0.4 dc Vg 0 1.5 0.01 Vb 0 -1.6 -0.4
* plotting * plotting
@ -53,7 +53,7 @@ plot I(Vs)
So we have two OSDI specific actions in the netlist: So we have two OSDI specific actions in the netlist:
load the model by load the model by
pre_osdi test_osdi_libs/bsimbulk.osdi pre_osdi osdi_libs/bsimbulk.osdi
instantiate the transistor by instantiate the transistor by
NMN1 dd gg ss bb BSIMBULK_osdi_N W=500n L=90n NMN1 dd gg ss bb BSIMBULK_osdi_N W=500n L=90n

2
examples/osdi/bsimbulk/bsimbulk_inverter.sp
View File

@ -27,7 +27,7 @@ c2 z vss 0.576f
.dc V1 0 'vcc' 'vcc/100' .dc V1 0 'vcc' 'vcc/100'
.control .control
pre_osdi test_osdi_libs/bsimbulk107.osdi pre_osdi osdi_libs/bsimbulk107.osdi
run run
*set nolegend *set nolegend
set xbrushwidth=3 set xbrushwidth=3

2
examples/osdi/bsimbulk/bsimbulk_ro.sp
View File

@ -31,7 +31,7 @@ c2 z vss 0.576f
.tran 10p 10n uic .tran 10p 10n uic
.control .control
pre_osdi test_osdi_libs/bsimbulk107.osdi pre_osdi osdi_libs/bsimbulk107.osdi
run run
set xbrushwidth=3 set xbrushwidth=3
plot in plot in

2
examples/osdi/bsimbulk/c7552_ann_bsimbulk.net
View File

@ -89225,7 +89225,7 @@ c2 z vss 0.834f
*.print tran V(g7529_1) V(g7509_0) V(g7484_1) V(g7477_1) V(g7460_0) V(g7503_1) V(g7522_0) V(g7485_1) V(g7453_0) V(g7474_0) V(g7500_0) V(g7514_0) V(g7546_1) V(g7549_0) V(g7467_0) V(g7491_0) V(g7456_0) V(g7495_1) V(g7545_0) V(g7473_0) V(g7541_0) V(g7448_1) V(g7525_1) V(g7550_1) V(g165_1) V(g7510_1) V(g7535_1) V(g7534_1) V(g7469_1) V(g7476_0) V(g7517_1) V(g7537_0) V(g7489_1) V(g7521_1) V(g7486_0) V(g7533_1) V(g7449_0) V(g7447_0) V(g7528_0) V(g7513_1) V(g7548_0) V(g7544_1) V(g7552_0) V(g7540_1) V(g7507_0) V(g7481_0) V(g7455_0) V(g7502_1) V(g7446_1) V(g7478_1) V(g7470_0) V(g7526_0) V(g7494_1) V(g7452_1) V(g7463_0) V(g7532_1) V(g7512_0) V(g7527_0) V(g7451_0) V(g7472_0) V(g7498_1) V(g7475_0) V(g7536_0) V(g7488_1) V(g7493_1) V(g7551_1) V(g7482_0) V(g7487_1) V(g7501_1) V(g7520_1) V(g7516_1) V(g7450_1) V(g7508_0) V(g7458_1) V(g7479_1) V(g7506_1) V(g7499_0) V(g7471_0) V(g7465_1) V(g7464_1) V(g7543_1) V(g7524_0) V(g7539_1) V(g7468_1) V(g7459_0) V(g7504_1) V(g7515_1) V(g7492_1) V(g7511_0) V(g7462_1) V(g7530_0) V(g7497_1) V(g7454_1) V(g7519_1) V(g7531_0) V(g7547_0) V(g7483_1) V(g7466_1) V(g7480_1) V(g7523_1) V(g7496_0) V(g7538_0) V(g7490_1) V(g7518_1) V(g7461_0) V(g7542_0) V(g7457_0) V(g7505_1) *.print tran V(g7529_1) V(g7509_0) V(g7484_1) V(g7477_1) V(g7460_0) V(g7503_1) V(g7522_0) V(g7485_1) V(g7453_0) V(g7474_0) V(g7500_0) V(g7514_0) V(g7546_1) V(g7549_0) V(g7467_0) V(g7491_0) V(g7456_0) V(g7495_1) V(g7545_0) V(g7473_0) V(g7541_0) V(g7448_1) V(g7525_1) V(g7550_1) V(g165_1) V(g7510_1) V(g7535_1) V(g7534_1) V(g7469_1) V(g7476_0) V(g7517_1) V(g7537_0) V(g7489_1) V(g7521_1) V(g7486_0) V(g7533_1) V(g7449_0) V(g7447_0) V(g7528_0) V(g7513_1) V(g7548_0) V(g7544_1) V(g7552_0) V(g7540_1) V(g7507_0) V(g7481_0) V(g7455_0) V(g7502_1) V(g7446_1) V(g7478_1) V(g7470_0) V(g7526_0) V(g7494_1) V(g7452_1) V(g7463_0) V(g7532_1) V(g7512_0) V(g7527_0) V(g7451_0) V(g7472_0) V(g7498_1) V(g7475_0) V(g7536_0) V(g7488_1) V(g7493_1) V(g7551_1) V(g7482_0) V(g7487_1) V(g7501_1) V(g7520_1) V(g7516_1) V(g7450_1) V(g7508_0) V(g7458_1) V(g7479_1) V(g7506_1) V(g7499_0) V(g7471_0) V(g7465_1) V(g7464_1) V(g7543_1) V(g7524_0) V(g7539_1) V(g7468_1) V(g7459_0) V(g7504_1) V(g7515_1) V(g7492_1) V(g7511_0) V(g7462_1) V(g7530_0) V(g7497_1) V(g7454_1) V(g7519_1) V(g7531_0) V(g7547_0) V(g7483_1) V(g7466_1) V(g7480_1) V(g7523_1) V(g7496_0) V(g7538_0) V(g7490_1) V(g7518_1) V(g7461_0) V(g7542_0) V(g7457_0) V(g7505_1)
.control .control
pre_osdi test_osdi_libs/bsimbulk107.osdi pre_osdi osdi_libs/bsimbulk107.osdi
unset ngdebug unset ngdebug
save V(g7529_1) V(g7509_0) V(g7484_1) V(g7477_1) V(g7460_0) V(g7503_1) V(g7522_0) V(g7485_1) V(g7453_0) V(g7474_0) V(g7500_0) V(g7514_0) V(g7546_1) V(g7549_0) V(g7467_0) V(g7491_0) V(g7456_0) V(g7495_1) V(g7545_0) V(g7473_0) V(g7541_0) V(g7448_1) V(g7525_1) V(g7550_1) V(g165_1) V(g7510_1) V(g7535_1) V(g7534_1) V(g7469_1) V(g7476_0) V(g7517_1) V(g7537_0) V(g7489_1) V(g7521_1) V(g7486_0) V(g7533_1) V(g7449_0) V(g7447_0) V(g7528_0) V(g7513_1) V(g7548_0) V(g7544_1) V(g7552_0) V(g7540_1) V(g7507_0) V(g7481_0) V(g7455_0) V(g7502_1) V(g7446_1) V(g7478_1) V(g7470_0) V(g7526_0) V(g7494_1) V(g7452_1) V(g7463_0) V(g7532_1) V(g7512_0) V(g7527_0) V(g7451_0) V(g7472_0) V(g7498_1) V(g7475_0) V(g7536_0) V(g7488_1) V(g7493_1) V(g7551_1) V(g7482_0) V(g7487_1) V(g7501_1) V(g7520_1) V(g7516_1) V(g7450_1) V(g7508_0) V(g7458_1) V(g7479_1) V(g7506_1) V(g7499_0) V(g7471_0) V(g7465_1) V(g7464_1) V(g7543_1) V(g7524_0) V(g7539_1) V(g7468_1) V(g7459_0) V(g7504_1) V(g7515_1) V(g7492_1) V(g7511_0) V(g7462_1) V(g7530_0) V(g7497_1) V(g7454_1) V(g7519_1) V(g7531_0) V(g7547_0) V(g7483_1) V(g7466_1) V(g7480_1) V(g7523_1) V(g7496_0) V(g7538_0) V(g7490_1) V(g7518_1) V(g7461_0) V(g7542_0) V(g7457_0) V(g7505_1) save V(g7529_1) V(g7509_0) V(g7484_1) V(g7477_1) V(g7460_0) V(g7503_1) V(g7522_0) V(g7485_1) V(g7453_0) V(g7474_0) V(g7500_0) V(g7514_0) V(g7546_1) V(g7549_0) V(g7467_0) V(g7491_0) V(g7456_0) V(g7495_1) V(g7545_0) V(g7473_0) V(g7541_0) V(g7448_1) V(g7525_1) V(g7550_1) V(g165_1) V(g7510_1) V(g7535_1) V(g7534_1) V(g7469_1) V(g7476_0) V(g7517_1) V(g7537_0) V(g7489_1) V(g7521_1) V(g7486_0) V(g7533_1) V(g7449_0) V(g7447_0) V(g7528_0) V(g7513_1) V(g7548_0) V(g7544_1) V(g7552_0) V(g7540_1) V(g7507_0) V(g7481_0) V(g7455_0) V(g7502_1) V(g7446_1) V(g7478_1) V(g7470_0) V(g7526_0) V(g7494_1) V(g7452_1) V(g7463_0) V(g7532_1) V(g7512_0) V(g7527_0) V(g7451_0) V(g7472_0) V(g7498_1) V(g7475_0) V(g7536_0) V(g7488_1) V(g7493_1) V(g7551_1) V(g7482_0) V(g7487_1) V(g7501_1) V(g7520_1) V(g7516_1) V(g7450_1) V(g7508_0) V(g7458_1) V(g7479_1) V(g7506_1) V(g7499_0) V(g7471_0) V(g7465_1) V(g7464_1) V(g7543_1) V(g7524_0) V(g7539_1) V(g7468_1) V(g7459_0) V(g7504_1) V(g7515_1) V(g7492_1) V(g7511_0) V(g7462_1) V(g7530_0) V(g7497_1) V(g7454_1) V(g7519_1) V(g7531_0) V(g7547_0) V(g7483_1) V(g7466_1) V(g7480_1) V(g7523_1) V(g7496_0) V(g7538_0) V(g7490_1) V(g7518_1) V(g7461_0) V(g7542_0) V(g7457_0) V(g7505_1)

2
examples/osdi/bsimbulk/netlist_mod_nmos.sp
View File

@ -15,7 +15,7 @@ VB bb 0 0
N1 dd gg ss bb BSIMBULK_osdi_N W=500n L=90n N1 dd gg ss bb BSIMBULK_osdi_N W=500n L=90n
.control .control
pre_osdi test_osdi_libs/bsimbulk107.osdi pre_osdi osdi_libs/bsimbulk107.osdi
set xbrushwidth=3 set xbrushwidth=3
* a DC sweep: drain, gate * a DC sweep: drain, gate
dc Vd 0 1.6 0.01 VG 0 1.6 0.2 dc Vd 0 1.6 0.01 VG 0 1.6 0.2

2
examples/osdi/bsimbulk/netlist_mod_pmos.sp
View File

@ -16,7 +16,7 @@ VB bb 0 0
N1 dd gg ss bb BSIMBULK_osdi_P W=500n L=90n N1 dd gg ss bb BSIMBULK_osdi_P W=500n L=90n
.control .control
pre_osdi test_osdi_libs/bsimbulk107.osdi pre_osdi osdi_libs/bsimbulk107.osdi
set xbrushwidth=3 set xbrushwidth=3
* a DC sweep: drain, gate * a DC sweep: drain, gate
*op *op

2
examples/osdi/bsimbulk/nmos_pmos_BSIMBULK.sp
View File

@ -17,7 +17,7 @@ vbsp 44 0 0
.control .control
* Load the models dynamically * Load the models dynamically
pre_osdi test_osdi_libs/bsimbulk107.osdi pre_osdi osdi_libs/bsimbulk107.osdi
set xgridwidth=2 set xgridwidth=2
set xbrushwidth=3 set xbrushwidth=3

0
examples/osdi/bsimbulk/test_osdi_libs/README → examples/osdi/bsimbulk/osdi_libs/README
View File

2
examples/osdi/bsimcmg/inverter_ro.sp
View File

@ -28,7 +28,7 @@ Xinv6 vi vo supply 0 mg_inv
.tran 0.1p 1n .tran 0.1p 1n
.control .control
pre_osdi test_osdi_libs/bsimcmg.osdi pre_osdi osdi_libs/bsimcmg.osdi
set xbrushwidth=3 set xbrushwidth=3
run run
plot i(vss) plot i(vss)

2
examples/osdi/bsimcmg/inverter_transient.sp
View File

@ -27,7 +27,7 @@ Xinv5 4 vo supply 0 mg_inv
.print tran v(vi) v(vo) .print tran v(vi) v(vo)
.control .control
pre_osdi test_osdi_libs/bsimcmg.osdi pre_osdi osdi_libs/bsimcmg.osdi
set xbrushwidth=3 set xbrushwidth=3
run run
plot v(vi) v(vo) plot v(vi) v(vo)

2
examples/osdi/bsimcmg/netlist_nmos.sp
View File

@ -16,7 +16,7 @@ VB bb 0 0
N1 dd gg ss bb BSIMCMG_osdi_N ; W=5u L=0.2u N1 dd gg ss bb BSIMCMG_osdi_N ; W=5u L=0.2u
.control .control
pre_osdi test_osdi_libs/bsimcmg.osdi pre_osdi osdi_libs/bsimcmg.osdi
set xbrushwidth=3 set xbrushwidth=3
* a DC sweep: drain, gate * a DC sweep: drain, gate
dc Vd 0 2.5 0.01 VG 0 2.5 0.5 dc Vd 0 2.5 0.01 VG 0 2.5 0.5

2
examples/osdi/bsimcmg/netlist_pmos.sp
View File

@ -16,7 +16,7 @@ VB bb 0 0
N1 dd gg ss bb BSIMCMG_osdi_P N1 dd gg ss bb BSIMCMG_osdi_P
.control .control
pre_osdi test_osdi_libs/bsimcmg.osdi pre_osdi osdi_libs/bsimcmg.osdi
set xbrushwidth=3 set xbrushwidth=3
* a DC sweep: drain, gate * a DC sweep: drain, gate
dc Vd 0 -1.8 -0.01 VG 0 -1.8 -0.3 dc Vd 0 -1.8 -0.01 VG 0 -1.8 -0.3

0
examples/osdi/bsimcmg/test_osdi_libs/README → examples/osdi/bsimcmg/osdi_libs/README
View File

2
examples/osdi/bsimcmg/ringosc_17stg.sp
View File

@ -45,7 +45,7 @@ Xinv17 17 1 supply 0 mg_inv
.measure tran delay_per_stage param='period/34' .measure tran delay_per_stage param='period/34'
.control .control
pre_osdi test_osdi_libs/bsimcmg.osdi pre_osdi osdi_libs/bsimcmg.osdi
set xbrushwidth=3 set xbrushwidth=3
run run
plot v(1) plot v(1)

2
examples/osdi/bsimcmg/simple_inverter_dc.sp
View File

@ -18,7 +18,7 @@ NN1 vout vin 0 0 BSIMCMG_osdi_N
.tran 10n 2u .tran 10n 2u
.control .control
pre_osdi test_osdi_libs/bsimcmg.osdi pre_osdi osdi_libs/bsimcmg.osdi
set xbrushwidth=3 set xbrushwidth=3
run run
plot v(vout) v(vin) plot v(vout) v(vin)

2
examples/osdi/hicuml0/DFF_Y_ECL_HICUM.sp
View File

@ -32,7 +32,7 @@ Rdt dt 0 1G
.include Modelcards/model-card-hicumL0V1p11_mod.lib .include Modelcards/model-card-hicumL0V1p11_mod.lib
.SAVE V(D) V(CLK) V(Q) .SAVE V(D) V(CLK) V(Q)
.control .control
pre_osdi test_osdi_libs/HICUML0-2.osdi pre_osdi osdi_libs/HICUML0-2.osdi
TRAN 0.25p 5n TRAN 0.25p 5n
rusage rusage
set color0=white set color0=white

2
examples/osdi/hicuml0/ECL-RO-5.cir
View File

@ -35,7 +35,7 @@ V1 VEE GND -5.2
.tran 0.02n 200n .tran 0.02n 200n
.control .control
pre_osdi test_osdi_libs/HICUML0-2.osdi pre_osdi osdi_libs/HICUML0-2.osdi
run run
rusage rusage
plot out9 xlimit 100n 110n plot out9 xlimit 100n 110n

2
examples/osdi/hicuml0/ECL-RO.cir
View File

@ -18,7 +18,7 @@ V3 In2 GND dc -1.75 pulse(-1.75 -0.9 0 1n 1n 2.5u 5u)
Rt1 DT GND 1G Rt1 DT GND 1G
.tran 0.1n 100u .tran 0.1n 100u
.control .control
pre_osdi test_osdi_libs/HICUML0-2.osdi pre_osdi osdi_libs/HICUML0-2.osdi
run run
plot a1 a2+2 in1+4 in2+6 plot a1 a2+2 in1+4 in2+6
.endc .endc

2
examples/osdi/hicuml0/hic0_gum.sp
View File

@ -8,7 +8,7 @@ XQ1 C B 0 S DT hicumL0V1p1_c_sbt
Rdt dt 0 1G Rdt dt 0 1G
.control .control
pre_osdi test_osdi_libs/HICUML0-2.osdi pre_osdi osdi_libs/HICUML0-2.osdi
dc vb 0.2 1.4 0.01 dc vb 0.2 1.4 0.01
set xbrushwidth=2 set xbrushwidth=2
plot abs(i(vc)) abs(i(vb)) abs(i(vs)) ylimit 0.1p 100m ylog plot abs(i(vc)) abs(i(vb)) abs(i(vs)) ylimit 0.1p 100m ylog

2
examples/osdi/hicuml0/hic0_out.sp
View File

@ -8,7 +8,7 @@ X1 C B 0 S DT hicumL0V1p1_c_sbt
Rdt dt 0 1G Rdt dt 0 1G
.control .control
pre_osdi test_osdi_libs/HICUML0-2.osdi pre_osdi osdi_libs/HICUML0-2.osdi
dc vc 0.0 3.0 0.05 ib 10u 100u 10u dc vc 0.0 3.0 0.05 ib 10u 100u 10u
set xbrushwidth=2 set xbrushwidth=2
plot abs(i(vc)) plot abs(i(vc))

0
examples/osdi/hicuml0/test_osdi_libs/README → examples/osdi/hicuml0/osdi_libs/README
View File

2
examples/osdi/mextram/mex_gum.sp
View File

@ -8,7 +8,7 @@ VS S 0 0.0
NQ1 C B 0 S dt BJTRF1 NQ1 C B 0 S dt BJTRF1
.control .control
pre_osdi test_osdi_libs/bjt504t.osdi pre_osdi osdi_libs/bjt504t.osdi
dc vb 0.2 1.4 0.01 dc vb 0.2 1.4 0.01
set xbrushwidth=2 set xbrushwidth=2
plot abs(i(vc)) abs(i(vb)) abs(i(vs)) ylog xlimit 0.3 1.4 ylimit 1e-12 100e-3 plot abs(i(vc)) abs(i(vb)) abs(i(vs)) ylog xlimit 0.3 1.4 ylimit 1e-12 100e-3

2
examples/osdi/mextram/mex_out.sp
View File

@ -8,7 +8,7 @@ VS S 0 0.0
NQ1 C B 0 S T BJTRF1 NQ1 C B 0 S T BJTRF1
.control .control
pre_osdi test_osdi_libs/bjt504t.osdi pre_osdi osdi_libs/bjt504t.osdi
dc vc 0 6.0 0.05 ib 0 8u 1u dc vc 0 6.0 0.05 ib 0 8u 1u
set xbrushwidth=2 set xbrushwidth=2
plot abs(i(vc)) xlabel Vce title Output-Characteristic plot abs(i(vc)) xlabel Vce title Output-Characteristic

0
examples/osdi/mextram/test_osdi_libs/README → examples/osdi/mextram/osdi_libs/README
View File

2
examples/osdi/mixed-models/bb-psp_ro.sp
View File

@ -67,7 +67,7 @@ c2 z vss 0.576f
.control .control
* Load the models dynamically * Load the models dynamically
pre_osdi test_osdi_libs/bsimbulk107.osdi test_osdi_libs/psp103.osdi pre_osdi osdi_libs/bsimbulk107.osdi osdi_libs/psp103.osdi
* Run the simulation * Run the simulation
run run
* Plotting * Plotting

2
examples/osdi/mixed-models/bsimbulk_inverter.sp
View File

@ -27,7 +27,7 @@ c2 z vss 0.576f
.dc V1 0 'vcc' 'vcc/100' .dc V1 0 'vcc' 'vcc/100'
.control .control
pre_osdi test_osdi_libs/bsimbulk107.osdi pre_osdi osdi_libs/bsimbulk107.osdi
run run
*set nolegend *set nolegend
set xbrushwidth=3 set xbrushwidth=3

0
examples/osdi/mixed-models/test_osdi_libs/README → examples/osdi/mixed-models/osdi_libs/README
View File

2
examples/osdi/mixed-models/psp_inverter.sp
View File

@ -53,7 +53,7 @@ c2 z vss 0.576f
.dc V1 0 'vcc' 'vcc/100' .dc V1 0 'vcc' 'vcc/100'
.control .control
pre_osdi test_osdi_libs/psp103.osdi pre_osdi osdi_libs/psp103.osdi
run run
*set nolegend *set nolegend
set xbrushwidth=2 set xbrushwidth=2

2
examples/osdi/psp103/c7552_ann_psp.net
View File

@ -89225,7 +89225,7 @@ c2 z vss 0.834f
*.print tran V(g7529_1) V(g7509_0) V(g7484_1) V(g7477_1) V(g7460_0) V(g7503_1) V(g7522_0) V(g7485_1) V(g7453_0) V(g7474_0) V(g7500_0) V(g7514_0) V(g7546_1) V(g7549_0) V(g7467_0) V(g7491_0) V(g7456_0) V(g7495_1) V(g7545_0) V(g7473_0) V(g7541_0) V(g7448_1) V(g7525_1) V(g7550_1) V(g165_1) V(g7510_1) V(g7535_1) V(g7534_1) V(g7469_1) V(g7476_0) V(g7517_1) V(g7537_0) V(g7489_1) V(g7521_1) V(g7486_0) V(g7533_1) V(g7449_0) V(g7447_0) V(g7528_0) V(g7513_1) V(g7548_0) V(g7544_1) V(g7552_0) V(g7540_1) V(g7507_0) V(g7481_0) V(g7455_0) V(g7502_1) V(g7446_1) V(g7478_1) V(g7470_0) V(g7526_0) V(g7494_1) V(g7452_1) V(g7463_0) V(g7532_1) V(g7512_0) V(g7527_0) V(g7451_0) V(g7472_0) V(g7498_1) V(g7475_0) V(g7536_0) V(g7488_1) V(g7493_1) V(g7551_1) V(g7482_0) V(g7487_1) V(g7501_1) V(g7520_1) V(g7516_1) V(g7450_1) V(g7508_0) V(g7458_1) V(g7479_1) V(g7506_1) V(g7499_0) V(g7471_0) V(g7465_1) V(g7464_1) V(g7543_1) V(g7524_0) V(g7539_1) V(g7468_1) V(g7459_0) V(g7504_1) V(g7515_1) V(g7492_1) V(g7511_0) V(g7462_1) V(g7530_0) V(g7497_1) V(g7454_1) V(g7519_1) V(g7531_0) V(g7547_0) V(g7483_1) V(g7466_1) V(g7480_1) V(g7523_1) V(g7496_0) V(g7538_0) V(g7490_1) V(g7518_1) V(g7461_0) V(g7542_0) V(g7457_0) V(g7505_1) *.print tran V(g7529_1) V(g7509_0) V(g7484_1) V(g7477_1) V(g7460_0) V(g7503_1) V(g7522_0) V(g7485_1) V(g7453_0) V(g7474_0) V(g7500_0) V(g7514_0) V(g7546_1) V(g7549_0) V(g7467_0) V(g7491_0) V(g7456_0) V(g7495_1) V(g7545_0) V(g7473_0) V(g7541_0) V(g7448_1) V(g7525_1) V(g7550_1) V(g165_1) V(g7510_1) V(g7535_1) V(g7534_1) V(g7469_1) V(g7476_0) V(g7517_1) V(g7537_0) V(g7489_1) V(g7521_1) V(g7486_0) V(g7533_1) V(g7449_0) V(g7447_0) V(g7528_0) V(g7513_1) V(g7548_0) V(g7544_1) V(g7552_0) V(g7540_1) V(g7507_0) V(g7481_0) V(g7455_0) V(g7502_1) V(g7446_1) V(g7478_1) V(g7470_0) V(g7526_0) V(g7494_1) V(g7452_1) V(g7463_0) V(g7532_1) V(g7512_0) V(g7527_0) V(g7451_0) V(g7472_0) V(g7498_1) V(g7475_0) V(g7536_0) V(g7488_1) V(g7493_1) V(g7551_1) V(g7482_0) V(g7487_1) V(g7501_1) V(g7520_1) V(g7516_1) V(g7450_1) V(g7508_0) V(g7458_1) V(g7479_1) V(g7506_1) V(g7499_0) V(g7471_0) V(g7465_1) V(g7464_1) V(g7543_1) V(g7524_0) V(g7539_1) V(g7468_1) V(g7459_0) V(g7504_1) V(g7515_1) V(g7492_1) V(g7511_0) V(g7462_1) V(g7530_0) V(g7497_1) V(g7454_1) V(g7519_1) V(g7531_0) V(g7547_0) V(g7483_1) V(g7466_1) V(g7480_1) V(g7523_1) V(g7496_0) V(g7538_0) V(g7490_1) V(g7518_1) V(g7461_0) V(g7542_0) V(g7457_0) V(g7505_1)
.control .control
pre_osdi test_osdi_libs/psp103.osdi pre_osdi osdi_libs/psp103.osdi
unset ngdebug unset ngdebug
save V(g7529_1) V(g7509_0) V(g7484_1) V(g7477_1) V(g7460_0) V(g7503_1) V(g7522_0) V(g7485_1) V(g7453_0) V(g7474_0) V(g7500_0) V(g7514_0) V(g7546_1) V(g7549_0) V(g7467_0) V(g7491_0) V(g7456_0) V(g7495_1) V(g7545_0) V(g7473_0) V(g7541_0) V(g7448_1) V(g7525_1) V(g7550_1) V(g165_1) V(g7510_1) V(g7535_1) V(g7534_1) V(g7469_1) V(g7476_0) V(g7517_1) V(g7537_0) V(g7489_1) V(g7521_1) V(g7486_0) V(g7533_1) V(g7449_0) V(g7447_0) V(g7528_0) V(g7513_1) V(g7548_0) V(g7544_1) V(g7552_0) V(g7540_1) V(g7507_0) V(g7481_0) V(g7455_0) V(g7502_1) V(g7446_1) V(g7478_1) V(g7470_0) V(g7526_0) V(g7494_1) V(g7452_1) V(g7463_0) V(g7532_1) V(g7512_0) V(g7527_0) V(g7451_0) V(g7472_0) V(g7498_1) V(g7475_0) V(g7536_0) V(g7488_1) V(g7493_1) V(g7551_1) V(g7482_0) V(g7487_1) V(g7501_1) V(g7520_1) V(g7516_1) V(g7450_1) V(g7508_0) V(g7458_1) V(g7479_1) V(g7506_1) V(g7499_0) V(g7471_0) V(g7465_1) V(g7464_1) V(g7543_1) V(g7524_0) V(g7539_1) V(g7468_1) V(g7459_0) V(g7504_1) V(g7515_1) V(g7492_1) V(g7511_0) V(g7462_1) V(g7530_0) V(g7497_1) V(g7454_1) V(g7519_1) V(g7531_0) V(g7547_0) V(g7483_1) V(g7466_1) V(g7480_1) V(g7523_1) V(g7496_0) V(g7538_0) V(g7490_1) V(g7518_1) V(g7461_0) V(g7542_0) V(g7457_0) V(g7505_1) save V(g7529_1) V(g7509_0) V(g7484_1) V(g7477_1) V(g7460_0) V(g7503_1) V(g7522_0) V(g7485_1) V(g7453_0) V(g7474_0) V(g7500_0) V(g7514_0) V(g7546_1) V(g7549_0) V(g7467_0) V(g7491_0) V(g7456_0) V(g7495_1) V(g7545_0) V(g7473_0) V(g7541_0) V(g7448_1) V(g7525_1) V(g7550_1) V(g165_1) V(g7510_1) V(g7535_1) V(g7534_1) V(g7469_1) V(g7476_0) V(g7517_1) V(g7537_0) V(g7489_1) V(g7521_1) V(g7486_0) V(g7533_1) V(g7449_0) V(g7447_0) V(g7528_0) V(g7513_1) V(g7548_0) V(g7544_1) V(g7552_0) V(g7540_1) V(g7507_0) V(g7481_0) V(g7455_0) V(g7502_1) V(g7446_1) V(g7478_1) V(g7470_0) V(g7526_0) V(g7494_1) V(g7452_1) V(g7463_0) V(g7532_1) V(g7512_0) V(g7527_0) V(g7451_0) V(g7472_0) V(g7498_1) V(g7475_0) V(g7536_0) V(g7488_1) V(g7493_1) V(g7551_1) V(g7482_0) V(g7487_1) V(g7501_1) V(g7520_1) V(g7516_1) V(g7450_1) V(g7508_0) V(g7458_1) V(g7479_1) V(g7506_1) V(g7499_0) V(g7471_0) V(g7465_1) V(g7464_1) V(g7543_1) V(g7524_0) V(g7539_1) V(g7468_1) V(g7459_0) V(g7504_1) V(g7515_1) V(g7492_1) V(g7511_0) V(g7462_1) V(g7530_0) V(g7497_1) V(g7454_1) V(g7519_1) V(g7531_0) V(g7547_0) V(g7483_1) V(g7466_1) V(g7480_1) V(g7523_1) V(g7496_0) V(g7538_0) V(g7490_1) V(g7518_1) V(g7461_0) V(g7542_0) V(g7457_0) V(g7505_1)

2
examples/osdi/psp103/nmos_pmos_PSP.sp
View File

@ -42,7 +42,7 @@ vbsp 44 0 0
.control .control
* Load the models dynamically * Load the models dynamically
pre_osdi test_osdi_libs/psp103.osdi pre_osdi osdi_libs/psp103.osdi
set xgridwidth=2 set xgridwidth=2
set xbrushwidth=3 set xbrushwidth=3

0
examples/osdi/psp103/test_osdi_libs/README → examples/osdi/psp103/osdi_libs/README
View File

2
examples/osdi/psp103/psp_inverter.sp
View File

@ -53,7 +53,7 @@ c2 z vss 0.576f
.dc V1 0 'vcc' 'vcc/100' .dc V1 0 'vcc' 'vcc/100'
.control .control
pre_osdi test_osdi_libs/psp103.osdi pre_osdi osdi_libs/psp103.osdi
run run
*set nolegend *set nolegend
set xbrushwidth=2 set xbrushwidth=2

2
examples/osdi/psp103/psp_out_nmos_nm.sp
View File

@ -23,7 +23,7 @@ nm1 d g s b nch
*.include Modelcards/psp103_nmos.mod *.include Modelcards/psp103_nmos.mod
.control .control
pre_osdi test_osdi_libs/psp103.osdi pre_osdi osdi_libs/psp103.osdi
dc vd 0 2.0 0.05 vg 0 1.5 0.25 dc vd 0 2.0 0.05 vg 0 1.5 0.25
plot i(vs) plot i(vs)
dc vg 0 1.5 0.05 vb 0 -3.0 -1 dc vg 0 1.5 0.05 vb 0 -3.0 -1

2
examples/osdi/psp103/psp_out_pmos_nm.sp
View File

@ -19,7 +19,7 @@ nm1 d g s b pch
* *
.option temp=21 .option temp=21
.control .control
pre_osdi test_osdi_libs/psp103.osdi pre_osdi osdi_libs/psp103.osdi
dc vd 0 -2.0 -0.05 vg 0 -1.5 -0.25 ; saturation dc vd 0 -2.0 -0.05 vg 0 -1.5 -0.25 ; saturation
plot i(vs) plot i(vs)
dc vg 0 -1.5 -0.05 vb 0 3.0 1 dc vg 0 -1.5 -0.05 vb 0 3.0 1

2
examples/osdi/psp103/psp_ro.sp
View File

@ -56,7 +56,7 @@ c2 z vss 0.576f
.tran 10p 10n uic .tran 10p 10n uic
.control .control
pre_osdi test_osdi_libs/psp103.osdi pre_osdi osdi_libs/psp103.osdi
run run
set xbrushwidth=3 set xbrushwidth=3
plot in plot in

2
examples/osdi/psp103/psp_transfer.sp
View File

@ -19,7 +19,7 @@ nm1 d g s b nch
* *
.option temp=21 .option temp=21
.control .control
pre_osdi test_osdi_libs/psp103.osdi pre_osdi osdi_libs/psp103.osdi
set xbrushwidth=2 set xbrushwidth=2
dc vg 0 1.5 0.02 vb -3 0 0.5 dc vg 0 1.5 0.02 vb -3 0 0.5
plot abs(i(vd)) plot abs(i(vd))

0
examples/osdi/r2_cmc/test_osdi_win/README → examples/osdi/r2_cmc/osdi_win/README
View File

2
examples/osdi/r2_cmc/res_r2_cmc.cir
View File

@ -7,7 +7,7 @@ NRr2_cmc 1 0 rmodel w=1u l=20u isnoisy=1
.model rmodel r2_cmc(level=2 rsh=200 xl=0.2u xw=-0.05u p3=0.12 q3=1.6 p2=0.015 q2=3.8 tc1=1.5e-4 tc2=7e-7) .model rmodel r2_cmc(level=2 rsh=200 xl=0.2u xw=-0.05u p3=0.12 q3=1.6 p2=0.015 q2=3.8 tc1=1.5e-4 tc2=7e-7)
.control .control
pre_osdi test_osdi_libs/r2_cmc.osdi pre_osdi osdi_libs/r2_cmc.osdi
op op
let res = v(1) / -v1#branch let res = v(1) / -v1#branch
print res print res