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Prevent VSRC PWL glitches: 

The fold is exact on paper, but floor() on a ratio of doubles can leave time a few ulp
PAST the last point: measured at 7.5e-23 s after about 1900 periods of a 1 ns clock.
The search below then matches no segment at all, drops out of the loop without assigning,
and the source silently keeps value's initialiser of 0 V for that one timepoint.
On a clock that is a dropout to zero in the middle of an edge -- a glitch a downstream
flip-flop reads as two extra edges, which is far worse than the tiny timing error it comes
from. Clamp so the last segment always matches.
This commit is contained in:
Alfredo Tomasini 2026-08-12 14:35:54 +02:00 committed by Holger Vogt
parent 5fd4fd1dfa
commit ba36e3bdc9
2 changed files with 6 additions and 0 deletions
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3
src/spicelib/devices/isrc/isrcload.c
View File

@ -322,6 +322,9 @@ ISRCload(GENmodel *inModel, CKTcircuit *ckt)
time -= here->ISRCcoeffs[here->ISRCrBreakpt];
time -= period * floor(time / period);
time += here->ISRCcoeffs[here->ISRCrBreakpt];
/* prevent glitches */
if (time > end_time)
time = end_time;
}
else {
value =

3
src/spicelib/devices/vsrc/vsrcload.c
View File

@ -351,6 +351,9 @@ VSRCload(GENmodel *inModel, CKTcircuit *ckt)
time -= here->VSRCcoeffs[here->VSRCrBreakpt];
time -= period * floor(time / period);
time += here->VSRCcoeffs[here->VSRCrBreakpt];
/* prevent glitches */
if (time > end_time)
time = end_time;
} else {
value =
here->VSRCcoeffs[here->VSRCfunctionOrder - 1];