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VDMOS added

This commit is contained in:
Holger Vogt 2018-05-19 22:29:28 +02:00
parent 09e3e76c71
commit b90c16f9c6
1 changed files with 12 additions and 0 deletions
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12
DEVICES
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@ -54,6 +54,7 @@ Table of contents
11.12 BSIM4 - BSIM model level 4 11.12 BSIM4 - BSIM model level 4
11.13 HiSIM2 - Hiroshima-University STARC IGFET Model 11.13 HiSIM2 - Hiroshima-University STARC IGFET Model
11.14 HiSIM_HV - Hiroshima-University STARC IGFET High Voltage Model 11.14 HiSIM_HV - Hiroshima-University STARC IGFET High Voltage Model
11.15 VDMOS - A simple PowerMOS transistor model derived from MOS1
12. SOI devices 12. SOI devices
12.1 BSIM3SOI_FD - SOI model (fully depleted devices) 12.1 BSIM3SOI_FD - SOI model (fully depleted devices)
12.2 BSIM3SOI_DD - SOI Model (dynamic depletion model) 12.2 BSIM3SOI_DD - SOI Model (dynamic depletion model)
@ -718,6 +719,17 @@ will be updated every time the device specific code is altered or changed to ref
Web site: http://home.hiroshima-u.ac.jp/usdl/HiSIM.html Web site: http://home.hiroshima-u.ac.jp/usdl/HiSIM.html
11.15 VDMOS - Simple PowerMOS model
Ver: 1
Class: M
Level: -
Dir: devices/vdmos
Status: TO BE TESTED.
This is a simplified Power MOS model, derived from MOS1 and
diode, similar to LTSPICE and SuperSpice VDMOS
12. SOI devices 12. SOI devices
12.1 BSIM3SOI_FD - SOI model (fully depleted devices) 12.1 BSIM3SOI_FD - SOI model (fully depleted devices)