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typo

This commit is contained in:
Holger Vogt 2026-07-17 10:43:02 +02:00
parent 3f7f438f0a
commit b8ae73d4a2
1 changed files with 1 additions and 1 deletions
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2
src/spicelib/devices/vsrc/vsrcload.c
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@ -144,7 +144,7 @@ VSRCload(GENmodel *inModel, CKTcircuit *ckt)
deltat = phase * PER;
while (deltat > 0)
deltat -= PER;
/* shift time by pase (neg. for pos. phase value) */
/* shift time by phase (neg. for pos. phase value) */
time += deltat;
}
else if (PHASE > 0.0) { /* 7th parameter is number of pulses */