Merge branch 'pre-master-47' into bt_dev

src/frontend/com_dl.c

@@ -15,7 +15,7 @@ if (wl && wl->wl_word)
     if (load_opus(wl->wl_word)) {
         fprintf(stderr, "Error: Library %s couldn't be loaded!\n", wl->wl_word);
         ft_spiniterror = TRUE;
-        ft_codemodelerror = TRUE;
+        ft_codemodelerror = copy(wl->wl_word);
         if (ft_stricterror) /* if set in spinit */
             controlled_exit(EXIT_BAD);
     }

src/frontend/inpcom.c

@@ -1111,8 +1111,9 @@ struct card *inp_readall(FILE *fp, const char *dir_name, const char* file_name,
             fprintf(stderr, "    Any of the following steps may fail, if Verilog A models are involved!.\n\n");
         }
         if (ft_codemodelerror) {
-            fprintf(stderr, "Warning: code models like analog.cm have not been loaded successfully.\n");
+            fprintf(stderr, "Warning: code models like %s have not been loaded successfully.\n", ft_codemodelerror);
             fprintf(stderr, "    Any of the following steps may fail, if code models are involved!.\n\n");
+            tfree(ft_codemodelerror);
         }
 
         struct nscope *root = inp_add_levels(working);

src/frontend/miscvars.c

@@ -18,9 +18,9 @@ bool ft_vecdb = FALSE;
 bool ft_simdb = FALSE;
 bool ft_evdb = FALSE;
 bool ft_grdb = FALSE;
-bool ft_gidb = FALSE;
 bool ft_controldb = FALSE;
 bool ft_asyncdb = FALSE;
+bool ft_shvecsearch = FALSE;
 
 char *ft_setkwords[] = {
 

src/frontend/options.c

@@ -25,7 +25,8 @@ bool ft_acctprint = FALSE, ft_noacctprint = FALSE, ft_listprint = FALSE;
 bool ft_nodesprint = FALSE, ft_optsprint = FALSE, ft_noinitprint = FALSE;
 bool ft_norefprint = FALSE;
 bool ft_ngdebug = FALSE, ft_nginfo = FALSE, ft_stricterror = FALSE, ft_spiniterror = FALSE;
-bool ft_codemodelerror = FALSE, ft_osdierror = FALSE;
+bool ft_osdierror = FALSE;
+char* ft_codemodelerror = NULL;
 
 static void setdb(char *str);
 static struct variable *cp_enqvec_as_var(const char *vec_name,
@@ -283,7 +284,7 @@ cp_usrset(struct variable *var, bool isset)
     if (eq(var->va_name, "debug")) {
         if (var->va_type == CP_BOOL) {
             cp_debug = ft_simdb = ft_parsedb = ft_evdb = ft_vecdb =
-                ft_grdb = ft_gidb = ft_controldb = isset;
+                ft_grdb = ft_controldb = isset;
         } else if (var->va_type == CP_LIST) {
             for (tv = var->va_vlist; tv; tv = tv->va_next)
                 if (var->va_type == CP_STRING)
@@ -477,12 +478,12 @@ setdb(char *str)
         ft_vecdb = TRUE;
     else if (eq(str, "graf"))
         ft_grdb = TRUE;
-    else if (eq(str, "ginterface"))
-        ft_gidb = TRUE;
     else if (eq(str, "control"))
         ft_controldb = TRUE;
     else if (eq(str, "async"))
         ft_asyncdb = TRUE;
+    else if (eq(str, "shvecsearch"))
+        ft_shvecsearch = TRUE;
     else
         fprintf(cp_err, "Warning: no such debug class %s\n", str);
 }

src/include/ngspice/fteext.h

@@ -238,7 +238,6 @@ extern bool ft_parsedb;
 extern bool ft_evdb;
 extern bool ft_vecdb;
 extern bool ft_grdb;
-extern bool ft_gidb;
 extern bool ft_controldb;
 extern bool ft_asyncdb;
 extern char *ft_setkwords[];
@@ -248,8 +247,9 @@ extern bool ft_ngdebug;
 extern bool ft_nginfo;
 extern bool ft_stricterror;
 extern bool ft_spiniterror;
-extern bool ft_codemodelerror;
+extern char *ft_codemodelerror;
 extern bool ft_osdierror;
+extern bool ft_shvecsearch;
 
 /* parse.c */
 

src/maths/ni/niconv.c

@@ -81,6 +81,15 @@ NIconvTest(CKTcircuit *ckt)
 
 #ifdef NEWCONV
     i = CKTconvTest(ckt);
+    /* The individual testers, called by CKTconvTest, set
+     * ckt->CKTnoncon and ckt->CKTtroubleElt appropriately. */
+    if (ckt->CKTnoncon != 0) {
+        ckt->CKTtroubleNode = 0;
+        return(1);
+    }
+    /* CKTconvTest early-returns nonzero 'i' on the first error
+     * in evaluating convergence (such as parameter out of range) so
+     * there may be untested devices that have not yet converged */
     if (i)
 	ckt->CKTtroubleNode = 0;
     return(i);

src/sharedspice.c

@@ -1181,7 +1181,7 @@ pvector_info  ngGet_Vec_Info(char* vecname)
 {
     struct dvec* newvec;
 
-    if (ft_ngdebug)
+    if (ft_shvecsearch)
         fprintf(stdout, "\nGet vector info: searching for vector '%s'\n", vecname);
 
     if (!is_initialized) {

src/spicelib/devices/asrc/asrcconv.c

@@ -32,7 +32,7 @@ ASRCconvTest(GENmodel *inModel, CKTcircuit *ckt)
             }
 
             for (i = 0; i < here->ASRCtree->numVars; i++)
-                asrc_vals[i] = ckt->CKTrhsOld[here->ASRCvars[i]];
+                asrc_vals[i] = ckt->CKTrhs[here->ASRCvars[i]];
 
             if (here->ASRCtree->IFeval(here->ASRCtree, ckt->CKTgmin, &rhs,
                                        asrc_vals, asrc_derivs) != OK)

tests/regression/misc/Makefile.am

@@ -1,7 +1,7 @@
 ## Process this file with automake to produce Makefile.in
 
 
-TESTS = bugs-1.cir bugs-2.cir dollar-1.cir empty-1.cir resume-1.cir log-functions-1.cir alter-vec.cir test-noise-2.cir test-noise-3.cir ac-zero.cir asrc-tc-1.cir asrc-tc-2.cir if-elseif.cir
+TESTS = bugs-1.cir bugs-2.cir dollar-1.cir empty-1.cir resume-1.cir log-functions-1.cir alter-vec.cir test-noise-2.cir test-noise-3.cir ac-zero.cir asrc-tc-1.cir asrc-tc-2.cir if-elseif.cir convergence.cir
 
 TESTS_ENVIRONMENT = ngspice_vpath=$(srcdir) $(SHELL) $(top_srcdir)/tests/bin/check.sh $(top_builddir)/src/ngspice