polish build with MODSIMD

configure.ac

@@ -1189,7 +1189,7 @@ AC_ARG_ENABLE([modsimd],
     [AS_HELP_STRING([--enable-modsimd], [Enable simd acceleration in some device models])])
 
 if test "x$enable_modsimd" = xyes; then
-    OPENMPSIMD_CFLAGS = "-fopenmp-simd"
+    OPENMPSIMD_CFLAGS="-fopenmp-simd"
     
     AC_MSG_CHECKING([for vector extension])
     AC_TRY_COMPILE([

src/spicelib/devices/bsim3v32/INSTALL

@@ -1,34 +1,28 @@
-BSIM3V32SIMD is to be used with ngspice version 32, or the current development branch as for July 2020.
-It might work with other versions as well.
-For installing BSIM3V3SIMD, the ngspice source code is required.
+This modified BSIM3V32 code is accelerated using SIMD vector processing.
+It is part of the 'simd' branch on the ngspice git repository, based on ngspice version 32+.
 
-Extraction:
-- go to ngspice source code tree at <ngspice>/src/spicelib/devices
-- extract BSIM3V32SIMD.tar.gz
-- this will replace and add files in the directory bsim3v32
+Compilation instructions for using the acceleration:
+----------------------------------------------------
+../configure --enable-modsimd CFLAGS="-O3 -march=native"
+make
 
-Compilation on a target computer supporting AVX2:
-- go to the base of ngspice source tree
-- run automake (or ./autogen.sh)
-- mkdir buildsimd
-- cd buildsimd
-- ../configure CFLAGS="-O3 -march=native" (add your configure flags as required)
-- make (the compiler must be a recent gcc or clang, other compilers not tested).
-- make install (or use directly the <ngspice>/buildsimd/src/ngspice binary)
+It is important to set the -march flag, otherwise the compiled code will be much slower.
+For target without vector processing, do not use --enable-modsimd.
 
 Usage:
+-----
 The new optimized model will be used automatically if you have any BSIM3V32 devices in your simulated circuit.
 For other devices models, there will be no speed-up at all.
 
 Notes:
+-----
 Compiling for architectures other than x86_64 with AVX2 was not tested.
 It should be possible if the target architecture supports vector processing for double precision floating point numbers with vector length of 4 or more.
-In file b3v32ldsimd.c, set USEX86INTRINSICS to 0 and modify definition of functions vec4_MAX, vec4_exp, vec4_log, vec4_sqrt, vec4_blend, vec4_fabs with an adequate implementation for your achitecture.
+Autoconf will detect if x84 AVX intrinsics is available. If not available, the code will fall back to a construct using omp simd compiler directives, which is slightly less efficient compared to the intrinsics.
 
 Compiling for vector length of 8 was not tested.
 It should be possible if the target architecture supports it.
 Change NSIMD value from 4 to 8 in bsim3v32def.h.
-In file b3v32ldsimd.c, provides new functions vec8_* for all functions vec4_*. 
 
 Anamosic Ballenegger Design, July 2020
 www.anamosic.com

src/spicelib/devices/bsim3v32/b3v32ldsimd.c

@@ -53,8 +53,6 @@
 #define DELTA_3 0.02
 #define DELTA_4 0.02
 
-#define USEX86INTRINSICS 1
-
 typedef double Vec4d __attribute__ ((vector_size (sizeof(double)*4), aligned (sizeof(double)*4)));
 typedef int64_t Vec4m __attribute__ ((vector_size (sizeof(double)*4), aligned (sizeof(double)*4)));
 
@@ -300,8 +298,9 @@ void vec4_CheckCollisions(Vec4m stateindexes, const char* msg)
 	}
 }
 
-
+#if NSIMD==8
 #include "b3v32ldsimd8d.c"
+#endif
 
 typedef float vecelem_t;