* src/spicelib/analysis/cktpzstr.c: Reversed a patch that went
in between ng-spice-0.2 and ng-spice-0.3 that eliminated the
following warnings: 'suggest parentheses around && within
||'. The parenthesis were not placed correctly, leading to
incorrect behaviour of the pole-zero analysis.
* tests/polezero/*.out: Changed the content of these files because
the bug that caused the incorrect pole-zero results have been
traced to src/spicelib/analysis/cktpzstr.c.
This commit is contained in:
arno
parent
d902e99d6d
commit
9b7d4b3187
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@ -1,3 +1,9 @@
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2000-07-28 Arno W. Peters <A.W.Peters@ieee.org>
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* tests/polezero/*.out: Changed the content of these files because
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the bug that caused the incorrect pole-zero results have been
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traced to src/spicelib/analysis/cktpzstr.c.
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2000-07-05 Arno W. Peters <A.W.Peters@ieee.org>
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* src/devices/dev.c: Added first_device() and next_device() to
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@ -1,3 +1,11 @@
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2000-07-28 Arno W. Peters <A.W.Peters@ieee.org>
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* cktpzstr.c: Reversed a patch that went in between ng-spice-0.2
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and ng-spice-0.3 that eliminated the following warnings: 'suggest
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parentheses around && within ||'. The parenthesis were not placed
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correctly, leading to incorrect behaviour of the pole-zero
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analysis.
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2000-05-22 Paolo Nenzi <p.nenzi@ieee.org>
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* cktpzstr.c, cktsens.c: Applied Widlok patches.
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@ -304,10 +304,10 @@ PZeval(int strat, PZtrial **set, PZtrial **new_trial_p)
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new_trial->s.real = (set[1]->s.real + set[2]->s.real) / 2.0;
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}
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} else if (CKTpzTrapped == 3) {
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if ((new_trial->s.real <= set[0]->s.real
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|| new_trial->s.real == set[1]->s.real)
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&& (new_trial->s.imag == set[1]->s.imag
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|| new_trial->s.real >= set[2]->s.real)) {
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if (new_trial->s.real <= set[0]->s.real
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|| new_trial->s.real == set[1]->s.real
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&& new_trial->s.imag == set[1]->s.imag
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|| new_trial->s.real >= set[2]->s.real) {
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#ifdef PZDEBUG
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DEBUG(1)
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fprintf(stderr,
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@ -481,7 +481,7 @@ int CKTpzStrat(PZtrial **set)
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/* minima in magnitude */
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/* Search for exact mag. minima, look for complex pair */
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suggestion = SYM;
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} else if ((a_mag > b_mag || a_mag == b_mag)
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} else if (a_mag > b_mag || a_mag == b_mag
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&& fabs(a) > fabs(b))
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suggestion = SPLIT_LEFT;
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else
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@ -556,8 +556,8 @@ CKTpzRunTrial(CKTcircuit *ckt, PZtrial **new_trialp, PZtrial **set)
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C_SUBEQ(diff_frac,p->s,new_trial->s);
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if ((diff_frac.real < 0.0
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|| diff_frac.real == 0.0) && diff_frac.imag < 0.0) {
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if (diff_frac.real < 0.0
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|| diff_frac.real == 0.0 && diff_frac.imag < 0.0) {
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prev = p;
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if (p->flags & ISAMINIMA)
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base = p;
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@ -705,7 +705,7 @@ CKTpzRunTrial(CKTcircuit *ckt, PZtrial **new_trialp, PZtrial **set)
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}
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}
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if ((error == E_SINGULAR || new_trial->f_raw.real == 0.0)
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if (error == E_SINGULAR || new_trial->f_raw.real == 0.0
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&& new_trial->f_raw.imag == 0.0) {
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new_trial->f_raw.real = 0.0;
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new_trial->f_raw.imag = 0.0;
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@ -941,8 +941,8 @@ CKTpzUpdateSet(PZtrial **set, PZtrial *new)
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set[0] = new;
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this_move = FAR_LEFT;
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} else if (new->s.real < set[1]->s.real) {
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if ((!CKTpzTrapped || new->mag_def < set[1]->mag_def
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|| new->mag_def == set[1]->mag_def)
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if (!CKTpzTrapped || new->mag_def < set[1]->mag_def
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|| new->mag_def == set[1]->mag_def
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&& fabs(new->f_def.real) < fabs(set[1]->f_def.real)) {
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/* Really should check signs, not just compare fabs( ) */
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set[2] = set[1]; /* XXX = set[2]->prev :: possible opt */
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@ -953,8 +953,8 @@ CKTpzUpdateSet(PZtrial **set, PZtrial *new)
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this_move = NEAR_LEFT;
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}
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} else if (new->s.real < set[2]->s.real) {
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if ((!CKTpzTrapped || new->mag_def < set[1]->mag_def
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|| new->mag_def == set[1]->mag_def)
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if (!CKTpzTrapped || new->mag_def < set[1]->mag_def
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|| new->mag_def == set[1]->mag_def
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&& fabs(new->f_def.real) < fabs(set[1]->f_def.real)) {
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/* Really should check signs, not just compare fabs( ) */
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set[0] = set[1];
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@ -3,3 +3,72 @@ Circuit: BRIDGE-T FILTER
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Circuit: BRIDGE-T FILTER
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Operating point information:
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Node Voltage
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---- -------
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V(3) 1.200000e+01
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V(2) 0.000000e+00
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V(1) 1.200000e+01
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Source Current
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------ -------
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v1#branch 0.000000e+00
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Capacitor models (Fixed capacitor)
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model C
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cj 0
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cjsw 0
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defw 1e-05
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narrow 0
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Resistor models (Simple linear resistor)
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model R
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rsh 0
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narrow 0
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tc1 0
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tc2 0
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defw 1e-05
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Capacitor: Fixed capacitor
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device c2 c1
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model C C
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capacitanc 1e-06 1e-06
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i 2.69e-312 2.69e-312
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p 2.69e-312 2.69e-312
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Resistor: Simple linear resistor
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device r4 r3
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model R R
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resistance 1e+03 1e+03
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ac 0 0
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i 0 0
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p 0 0
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Vsource: Independent voltage source
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device v1
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dc 12
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acmag 1
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i 0
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p -0
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BRIDGE-T FILTER
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--------------------------------------------------------------------------------
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Index pole(1) pole(2)
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--------------------------------------------------------------------------------
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0 -2.618034e+03, 0.000000e+00 -3.819660e+02, 0.000000e+00
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BRIDGE-T FILTER
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--------------------------------------------------------------------------------
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Index zero(1) zero(2)
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--------------------------------------------------------------------------------
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0 -1.000000e+03, 0.000000e+00 -1.000000e+03, 0.000000e+00
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@ -3,3 +3,19 @@ Circuit: Multistage filter
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Circuit: Multistage filter
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Multistage filter
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--------------------------------------------------------------------------------
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Index pole(1) pole(2)
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--------------------------------------------------------------------------------
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0 -5.000000e+10, 0.000000e+00 -8.000000e+08, 0.000000e+00
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Multistage filter
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--------------------------------------------------------------------------------
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Index pole(3)
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--------------------------------------------------------------------------------
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0 -1.000000e+08, 0.000000e+00
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@ -3,3 +3,13 @@ Circuit: RC filter
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Circuit: RC filter
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RC filter
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--------------------------------------------------------------------------------
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Index all
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--------------------------------------------------------------------------------
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0 -1.000000e+08, 0.000000e+00
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