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bsimcmg, benchmark, try to run cfrgeo.sp rdsgeo.sp and noise.sp

This commit is contained in:
rlar 2017-07-23 22:01:52 +02:00 committed by Holger Vogt
parent e92d5c481e
commit 99b0b86dc7
3 changed files with 93 additions and 38 deletions
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47
bsimcmg_benchmark_test/cfrgeo.sp
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@ -1,14 +1,15 @@
*Sample netlist for BSIM-MG
* (exec-spice "ngspice %s" t)
* Geometry-dependent Cfr
*
.option abstol=1e-6 reltol=1e-6 post ingold
.temp 27
.hdl "bsimcmg.va"
*.hdl "bsimcmg.va"
.param hfin=30n
.model nmos2 bsimcmg
.model nmos2 NMOS level=17
+ DEVTYPE=1
+ CGEOMOD=2
+ HEPI=10n
@ -28,22 +29,40 @@ vgs gate 0 dc=0
vbs bulk 0 dc=0
* --- Transistor ---
X1 supply gate 0 bulk nmos2 TFIN=10n L=30n NFIN=1 FPITCH=20n LRSD=40n
X2 supply gate 0 bulk nmos2 TFIN=10n L=30n NFIN=1 FPITCH=40n LRSD=40n
X3 supply gate 0 bulk nmos2 TFIN=10n L=30n NFIN=1 FPITCH=60n LRSD=40n
X4 supply gate 0 bulk nmos2 TFIN=10n L=30n NFIN=1 FPITCH=80n LRSD=40n
M1 supply gate 0 bulk 0 nmos2 TFIN=10n L=30n NFIN=1 FPITCH=20n LRSD=40n
M2 supply gate 0 bulk 0 nmos2 TFIN=10n L=30n NFIN=1 FPITCH=40n LRSD=40n
M3 supply gate 0 bulk 0 nmos2 TFIN=10n L=30n NFIN=1 FPITCH=60n LRSD=40n
M4 supply gate 0 bulk 0 nmos2 TFIN=10n L=30n NFIN=1 FPITCH=80n LRSD=40n
* --- DC Analysis ---
.dc vgs 0.0 1.0 1.5
.print dc par'hfin' X1:CFGEO X2:CFGEO X3:CFGEO X4:CFGEO
.dc vgs 0.0 1.0 0.1
*.print dc par'hfin' M1:CFGEO M2:CFGEO M3:CFGEO M4:CFGEO
.alter
.param hfin=40n
.control
save @m1[CFGEO] @m2[CFGEO] @m3[CFGEO] @m4[CFGEO]
.alter
.param hfin=50n
showmod #nmos2 : HFIN
run
plot @m1[CFGEO] @m2[CFGEO] @m3[CFGEO] @m4[CFGEO]
.alter
.param hfin=60n
reset
altermod nmos2 hfin = 40n
showmod #nmos2 : HFIN
run
plot @m1[CFGEO] @m2[CFGEO] @m3[CFGEO] @m4[CFGEO]
reset
altermod nmos2 hfin = 50n
showmod #nmos2 : HFIN
run
plot @m1[CFGEO] @m2[CFGEO] @m3[CFGEO] @m4[CFGEO]
reset
altermod nmos2 hfin = 60n
showmod #nmos2 : HFIN
run
plot @m1[CFGEO] @m2[CFGEO] @m3[CFGEO] @m4[CFGEO]
.endc
.end

36
bsimcmg_benchmark_test/noise.sp
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@ -1,10 +1,11 @@
*Samle netlist for BSIM-MG
* (exec-spice "ngspice %s" t)
* Drain Noise Simulation
.option abstol=1e-6 reltol=1e-6 post ingold
.temp 27
.hdl "bsimcmg.va"
*.hdl "bsimcmg.va"
.include "modelcard.nmos"
* --- Voltage Sources ---
@ -16,17 +17,32 @@ vbs bulk 0 dc=0v
lbias 1 drain 1m
cload drain 2 1m
rload 2 0 R=1 noise=0
X1 drain gate 0 bulk nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
M1 drain gate 0 bulk 0 nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
+ FPITCH = 4.00E-08
* --- Analysis ---
.op
*.dc vgs -0.5 1.5 0.01
*.print dc i(lbias)
.ac dec 11 1k 100g
.noise v(drain) vgs 1
*.print ac i(cload)
.print ac v(drain)
.print noise inoise onoise
*.op
**.dc vgs -0.5 1.5 0.01
**.print dc i(lbias)
*.ac dec 11 1k 100g
*.noise v(drain) vgs 1
**.print ac i(cload)
*.print ac v(drain)
*.print noise inoise onoise
.control
op
reset
ac dec 11 1k 100g
plot vdb(drain)
reset
noise v(drain) vgs dec 11 1k 100g
print all
echo "silence in the studio, no noise today"
.endc
.end

48
bsimcmg_benchmark_test/rdsgeo.sp
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@ -1,12 +1,13 @@
*Sample netlist for BSIM-MG
* (exec-spice "ngspice %s" t)
* Geometry-dependent Rds
.option abstol=1e-6 reltol=1e-6 post ingold
.temp 27
.hdl "bsimcmg.va"
*.hdl "bsimcmg.va"
.model nmos2 bsimcmg
.model nmos2 NMOS level=17
+ DEVTYPE=1
+ RGEOMOD=1
+ HEPI=15n
@ -18,7 +19,7 @@
+ NSD=2.0e+26
+ LINT = 0
.model pmos2 bsimcmg
.model pmos2 PMOS level=17
+ DEVTYPE=0
+ RGEOMOD=1
+ HEPI=15n
@ -38,21 +39,40 @@ vgs gate 0 dc=0
vbs bulk 0 dc=0
* --- Transistor ---
Xn1 supply gate 0 bulk nmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=20n
Xn2 supply gate 0 bulk nmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=40n
Xn3 supply gate 0 bulk nmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=60n
Xn4 supply gate 0 bulk nmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=80n
Xp1 supply gate 0 bulk pmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=20n
Xp2 supply gate 0 bulk pmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=40n
Xp3 supply gate 0 bulk pmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=60n
Xp4 supply gate 0 bulk pmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=80n
Mn1 supply gate 0 bulk 0 nmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp LRSD=20n
Mn2 supply gate 0 bulk 0 nmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp LRSD=40n
Mn3 supply gate 0 bulk 0 nmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp LRSD=60n
Mn4 supply gate 0 bulk 0 nmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp LRSD=80n
Mp1 supply gate 0 bulk 0 pmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp LRSD=20n
Mp2 supply gate 0 bulk 0 pmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp LRSD=40n
Mp3 supply gate 0 bulk 0 pmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp LRSD=60n
Mp4 supply gate 0 bulk 0 pmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp LRSD=80n
* --- DC Analysis ---
.dc vgs 0.0 1.0 2.0
.dc vgs 0.0 1.0 0.1
.print dc Xn1:RSGEO Xn2:RSGEO Xn3:RSGEO Xn4:RSGEO
.print dc Xp1:RSGEO Xp2:RSGEO Xp3:RSGEO Xp4:RSGEO
.alter
.param fp=90n
.control
save @Mn1[RSGEO] @Mn2[RSGEO] @Mn3[RSGEO] @Mn4[RSGEO]
save @Mp1[RSGEO] @Mp2[RSGEO] @Mp3[RSGEO] @Mp4[RSGEO]
run
plot @Mn1[RSGEO] @Mn2[RSGEO] @Mn3[RSGEO] @Mn4[RSGEO]
plot @Mp1[RSGEO] @Mp2[RSGEO] @Mp3[RSGEO] @Mp4[RSGEO]
reset
alter @mn1[FPITCH] = 90n
alter @mn2[FPITCH] = 90n
alter @mn3[FPITCH] = 90n
alter @mn4[FPITCH] = 90n
alter @mp1[FPITCH] = 90n
alter @mp2[FPITCH] = 90n
alter @mp3[FPITCH] = 90n
alter @mp4[FPITCH] = 90n
run
plot @Mn1[RSGEO] @Mn2[RSGEO] @Mn3[RSGEO] @Mn4[RSGEO]
plot @Mp1[RSGEO] @Mp2[RSGEO] @Mp3[RSGEO] @Mp4[RSGEO]
.endc
.end