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PULSE: correct timing in case of phase != 0

This commit is contained in:
h_vogt 2010-11-21 00:32:54 +00:00
parent 39fccad193
commit 95b7a297fa
1 changed files with 1 additions and 1 deletions
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2
src/spicelib/devices/vsrc/vsrcacct.c
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@ -74,7 +74,7 @@ VSRCaccept(CKTcircuit *ckt, GENmodel *inModel)
#endif #endif
/* offset time by delay and limit to zero */ /* offset time by delay and limit to zero */
time = ckt->CKTtime - TD; time = ckt->CKTtime - TD;
tshift = TD;
#ifdef XSPICE #ifdef XSPICE
/* normalize phase to 0 - 2PI */ /* normalize phase to 0 - 2PI */
phase = PHASE * M_PI / 180.0; phase = PHASE * M_PI / 180.0;