PULSE: correct timing in case of phase != 0

2010-11-21 00:32:54 +00:00 · 2010-11-21 00:32:54 +00:00 · 95b7a297fa
parent 39fccad193
commit 95b7a297fa
1 changed files with 1 additions and 1 deletions
--- a/src/spicelib/devices/vsrc/vsrcacct.c
+++ b/src/spicelib/devices/vsrc/vsrcacct.c
@ -74,7 +74,7 @@ VSRCaccept(CKTcircuit *ckt, GENmodel *inModel)
 #endif
                    /* offset time by delay  and limit to zero */
                    time = ckt->CKTtime - TD;
-
+                    tshift = TD;
 #ifdef XSPICE					
 		     /* normalize phase to 0 - 2PI */ 
                    phase = PHASE * M_PI / 180.0;