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Fix the case when only one model supports CUDA for RHS and one model doesn't support CUDA at all

This commit is contained in:
Francesco Lannutti 2018-04-23 01:55:34 +02:00
parent d0803e5ed6
commit 94b7b82b73
4 changed files with 39 additions and 36 deletions
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6
src/spicelib/analysis/CUSPICE/cucktsetup.c
View File

@ -76,7 +76,7 @@ CKTcircuit *ckt
size2 = (long unsigned int)ckt->CKTnumStates ;
size3 = (long unsigned int)ckt->total_n_timeSteps ;
if (TopologyNNZ > 0 || TopologyNNZRHS > 0) {
if (ckt->total_n_Ptr > 0 || TopologyNNZRHS > 0) {
/* Topology Matrix Handling */
status = cudaMalloc ((void **)&(ckt->CKTmatrix->d_CKTrhs), (n + 1) * sizeof(double)) ;
CUDAMALLOCCHECK (ckt->CKTmatrix->d_CKTrhs, (n + 1), double, status)
@ -90,7 +90,7 @@ CKTcircuit *ckt
status = cudaMalloc ((void **)&(ckt->d_CKTloadOutputRHS), mRHS * sizeof(double)) ;
CUDAMALLOCCHECK (ckt->d_CKTloadOutputRHS, mRHS, double, status)
if (TopologyNNZ > 0) {
if (ckt->total_n_Ptr > 0) {
status = cudaMalloc ((void **)&(ckt->d_CKTtopologyMatrixCSRp), (nz + 1) * sizeof(int)) ;
CUDAMALLOCCHECK (ckt->d_CKTtopologyMatrixCSRp, (nz + 1), int, status)
@ -114,7 +114,7 @@ CKTcircuit *ckt
cudaMemset (ckt->d_CKTloadOutput + ckt->total_n_values, 0, sizeof(double)) ; //DiagGmin is 0 at the beginning
if (TopologyNNZ > 0) {
if (ckt->total_n_Ptr > 0) {
status = cudaMemcpy (ckt->d_CKTtopologyMatrixCSRp, ckt->CKTtopologyMatrixCSRp, (nz + 1) * sizeof(int), cudaMemcpyHostToDevice) ;
CUDAMEMCPYCHECK (ckt->d_CKTtopologyMatrixCSRp, (nz + 1), int, status)

5
src/spicelib/analysis/CUSPICE/cucktsystem.c
View File

@ -56,6 +56,11 @@ CKTcircuit *ckt
/* Copy back the Matrix */
status = cudaMemcpy (ckt->CKTmatrix->CKTkluAx, ckt->CKTmatrix->d_CKTkluAx, nz * sizeof(double), cudaMemcpyDeviceToHost) ;
CUDAMEMCPYCHECK (ckt->CKTmatrix->CKTkluAx, nz, double, status)
} else {
/* Matrix is empty */
for (i = 0 ; i < nz ; i++) {
ckt->CKTmatrix->CKTkluAx [i] = 0 ;
}
}
if (ckt->total_n_PtrRHS > 0) {

20
src/spicelib/analysis/cktload.c
View File

@ -137,19 +137,19 @@ CKTload(CKTcircuit *ckt)
int TopologyNNZ, TopologyNNZRHS ;
TopologyNNZ = ckt->total_n_Ptr + ckt->CKTdiagElements ; // + ckt->CKTdiagElements because of CKTdiagGmin
// without the zeroes along the diagonal
// without the zeroes along the diagonal
TopologyNNZRHS = ckt->total_n_PtrRHS ;
if (TopologyNNZ > 0 || TopologyNNZRHS > 0) {
/* Copy the CKTdiagGmin value to the GPU */
// The real Gmin is needed only when the matrix will reside entirely on the GPU
// Right now, only some models support CUDA, so the matrix is only partially created on the GPU
cudaMemset (ckt->d_CKTloadOutput + ckt->total_n_values, 0, sizeof(double)) ;
//cudaError_t statusMemcpy ;
//statusMemcpy = cudaMemcpy (ckt->d_CKTloadOutput + ckt->total_n_values, &(ckt->CKTdiagGmin), sizeof(double), cudaMemcpyHostToDevice) ;
//CUDAMEMCPYCHECK (ckt->d_CKTloadOutput + ckt->total_n_values, 1, double, statusMemcpy)
if (ckt->total_n_Ptr > 0 || TopologyNNZRHS > 0) {
if (ckt->total_n_Ptr > 0) {
/* Copy the CKTdiagGmin value to the GPU */
// The real Gmin is needed only when the matrix will reside entirely on the GPU
// Right now, only some models support CUDA, so the matrix is only partially created on the GPU
cudaMemset (ckt->d_CKTloadOutput + ckt->total_n_values, 0, sizeof(double)) ;
//cudaError_t statusMemcpy ;
//statusMemcpy = cudaMemcpy (ckt->d_CKTloadOutput + ckt->total_n_values, &(ckt->CKTdiagGmin), sizeof(double), cudaMemcpyHostToDevice) ;
//CUDAMEMCPYCHECK (ckt->d_CKTloadOutput + ckt->total_n_values, 1, double, statusMemcpy)
if (TopologyNNZ > 0) {
/* Performing CSRMV for the Sparse Matrix using CUSPARSE */
cusparseStatus = cusparseDcsrmv ((cusparseHandle_t)(ckt->CKTmatrix->CKTcsrmvHandle),
CUSPARSE_OPERATION_NON_TRANSPOSE,

44
src/spicelib/analysis/cktsetup.c
View File

@ -236,32 +236,30 @@ CKTsetup(CKTcircuit *ckt)
// without the zeroes along the diagonal
TopologyNNZRHS = ckt->total_n_PtrRHS ;
if (TopologyNNZ > 0 || TopologyNNZRHS > 0) {
if (ckt->total_n_Ptr > 0 || TopologyNNZRHS > 0) {
/* Topology Matrix Construction & Topology Matrix for the RHS Construction */
if (TopologyNNZ > 0 || TopologyNNZRHS > 0) {
if (TopologyNNZ > 0) {
/* Topology Matrix Pre-Allocation in COO format */
ckt->CKTtopologyMatrixCOOi = TMALLOC (int, TopologyNNZ) ;
ckt->CKTtopologyMatrixCOOj = TMALLOC (int, TopologyNNZ) ;
ckt->CKTtopologyMatrixCOOx = TMALLOC (double, TopologyNNZ) ;
}
if (TopologyNNZRHS > 0) {
/* Topology Matrix for the RHS Pre-Allocation in COO format */
ckt->CKTtopologyMatrixCOOiRHS = TMALLOC (int, TopologyNNZRHS) ;
ckt->CKTtopologyMatrixCOOjRHS = TMALLOC (int, TopologyNNZRHS) ;
ckt->CKTtopologyMatrixCOOxRHS = TMALLOC (double, TopologyNNZRHS) ;
}
u = 0 ;
uRHS = 0 ;
for (i = 0 ; i < DEVmaxnum ; i++)
if (DEVices [i] && DEVices [i]->DEVtopology && ckt->CKThead [i])
DEVices [i]->DEVtopology (ckt->CKThead [i], ckt, &u, &uRHS) ;
if (ckt->total_n_Ptr > 0) {
/* Topology Matrix Pre-Allocation in COO format */
ckt->CKTtopologyMatrixCOOi = TMALLOC (int, TopologyNNZ) ;
ckt->CKTtopologyMatrixCOOj = TMALLOC (int, TopologyNNZ) ;
ckt->CKTtopologyMatrixCOOx = TMALLOC (double, TopologyNNZ) ;
}
if (ckt->CKTdiagElements > 0) {
if (TopologyNNZRHS > 0) {
/* Topology Matrix for the RHS Pre-Allocation in COO format */
ckt->CKTtopologyMatrixCOOiRHS = TMALLOC (int, TopologyNNZRHS) ;
ckt->CKTtopologyMatrixCOOjRHS = TMALLOC (int, TopologyNNZRHS) ;
ckt->CKTtopologyMatrixCOOxRHS = TMALLOC (double, TopologyNNZRHS) ;
}
u = 0 ;
uRHS = 0 ;
for (i = 0 ; i < DEVmaxnum ; i++)
if (DEVices [i] && DEVices [i]->DEVtopology && ckt->CKThead [i])
DEVices [i]->DEVtopology (ckt->CKThead [i], ckt, &u, &uRHS) ;
if (ckt->total_n_Ptr > 0) {
/* CKTdiagGmin Contribute Addition to the Topology Matrix */
k = u ;
for (j = 0 ; j < n ; j++)
@ -278,7 +276,7 @@ CKTsetup(CKTcircuit *ckt)
/* Copy the Topology Matrix to the GPU in COO format */
if (TopologyNNZ > 0) {
if (ckt->total_n_Ptr > 0) {
/* COO format to CSR format Conversion using Quick Sort */
Element *TopologyStruct ;