(testing) simplify test cases, fix bug
This commit is contained in:
Markus Mueller
DSPOM
parent
deb33cbe8e
commit
92aea309ec
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@ -0,0 +1,367 @@
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/*
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* Copyright© 2022 SemiMod UG. All rights reserved.
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*
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* This is an exemplary implementation of the OSDI interface for the Verilog-A
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* model specified in diode.va. In the future, the OpenVAF compiler shall
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* generate an comparable object file. Primary purpose of this is example to
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* have a concrete example for the OSDI interface, OpenVAF will generate a more
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* optimized implementation.
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*
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*/
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#include "osdi.h"
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#include "string.h"
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#include <math.h>
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#include <stdbool.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <stdio.h>
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// public interface
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extern uint32_t OSDI_VERSION_MAJOR;
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extern uint32_t OSDI_VERSION_MINOR;
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extern uint32_t OSDI_NUM_DESCRIPTORS;
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extern OsdiDescriptor OSDI_DESCRIPTORS[1];
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// number of nodes and definitions of node ids for nicer syntax in this file
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// note: order should be same as "nodes" list defined later
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#define NUM_NODES 3
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#define P 0
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#define M 1
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// number of matrix entries and definitions for Jacobian entries for nicer
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// syntax in this file
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#define NUM_MATRIX 4
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#define P_P 0
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#define P_M 1
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#define M_P 2
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#define M_M 3
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// The model structure for the diode
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typedef struct CapacitorModel
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{
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double C;
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bool C_given;
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} CapacitorModel;
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// The instace structure for the diode
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typedef struct CapacitorInstance
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{
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double temperature;
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double rhs_resist[NUM_NODES];
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double rhs_react[NUM_NODES];
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double jacobian_resist[NUM_MATRIX];
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double jacobian_react[NUM_MATRIX];
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double *jacobian_ptr_resist[NUM_MATRIX];
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double *jacobian_ptr_react[NUM_MATRIX];
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uint32_t node_off[NUM_NODES];
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} CapacitorInstance;
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// implementation of the access function as defined by the OSDI spec
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void *osdi_access(void *inst_, void *model_, uint32_t id, uint32_t flags)
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{
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CapacitorModel *model = (CapacitorModel *)model_;
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CapacitorInstance *inst = (CapacitorInstance *)inst_;
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bool *given;
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void *value;
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switch (id) // id of params defined in param_opvar array
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{
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case 0:
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value = (void *)&model->C;
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given = &model->C_given;
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break;
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default:
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return NULL;
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}
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if (flags & ACCESS_FLAG_SET)
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{
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*given = true;
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}
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return value;
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}
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// implementation of the setup_model function as defined in the OSDI spec
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OsdiInitInfo setup_model(void *_handle, void *model_)
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{
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CapacitorModel *model = (CapacitorModel *)model_;
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// set parameters and check bounds
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if (!model->C_given)
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{
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model->C = 1e-15;
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}
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return (OsdiInitInfo){.flags = 0, .num_errors = 0, .errors = NULL};
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}
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// implementation of the setup_instace function as defined in the OSDI spec
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OsdiInitInfo setup_instance(void *_handle, void *inst_, void *model_,
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double temperature, uint32_t _num_terminals)
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{
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CapacitorInstance *inst = (CapacitorInstance *)inst_;
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CapacitorModel *model = (CapacitorModel *)model_;
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inst->temperature = temperature;
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return (OsdiInitInfo){.flags = 0, .num_errors = 0, .errors = NULL};
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}
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// implementation of the eval function as defined in the OSDI spec
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uint32_t eval(void *handle, void *inst_, void *model_, uint32_t flags,
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double *prev_solve, OsdiSimParas *sim_params)
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{
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CapacitorModel *model = (CapacitorModel *)model_;
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CapacitorInstance *inst = (CapacitorInstance *)inst_;
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// get voltages
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double vp = prev_solve[inst->node_off[P]];
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double vm = prev_solve[inst->node_off[M]];
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double vpm = vp - vm;
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double gmin = 1e-12;
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for (int i = 0; sim_params->names[i] != NULL; i++)
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{
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if (strcmp(sim_params->names[i], "gmin") == 0)
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{
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gmin = sim_params->vals[i];
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}
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}
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double qc_vpm = model->C;
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double qc = model->C * vpm;
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////////////////////////////////
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// evaluate model equations
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////////////////////////////////
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if (flags & CALC_REACT_RESIDUAL)
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{
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// write react rhs
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inst->rhs_react[P] = qc;
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inst->rhs_react[M] = -qc;
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}
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//////////////////
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// write Jacobian
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//////////////////
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if (flags & CALC_REACT_JACOBIAN)
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{
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// write react matrix
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// stamp Qd between nodes A and Ci depending also on dT
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inst->jacobian_react[P_P] = qc_vpm;
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inst->jacobian_react[P_M] = -qc_vpm;
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inst->jacobian_react[M_P] = -qc_vpm;
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inst->jacobian_react[M_M] = qc_vpm;
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}
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return 0;
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}
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// TODO implementation of the load_noise function as defined in the OSDI spec
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void load_noise(void *inst, void *model, double freq, double *noise_dens,
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double *ln_noise_dens)
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{
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// TODO add noise to example
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}
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#define LOAD_RHS_RESIST(name) \
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dst[inst->node_off[name]] += inst->rhs_resist[name];
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// implementation of the load_rhs_resist function as defined in the OSDI spec
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void load_residual_resist(void *inst_, double *dst)
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{
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CapacitorInstance *inst = (CapacitorInstance *)inst_;
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LOAD_RHS_RESIST(P)
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LOAD_RHS_RESIST(M)
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}
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#define LOAD_RHS_REACT(name) dst[inst->node_off[name]] += inst->rhs_react[name];
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// implementation of the load_rhs_react function as defined in the OSDI spec
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void load_residual_react(void *inst_, double *dst)
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{
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CapacitorInstance *inst = (CapacitorInstance *)inst_;
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LOAD_RHS_REACT(P)
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LOAD_RHS_REACT(M)
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}
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#define LOAD_MATRIX_RESIST(name) \
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*inst->jacobian_ptr_resist[name] += inst->jacobian_resist[name];
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// implementation of the load_matrix_resist function as defined in the OSDI spec
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void load_jacobian_resist(void *inst_)
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{
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CapacitorInstance *inst = (CapacitorInstance *)inst_;
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LOAD_MATRIX_RESIST(P_P)
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LOAD_MATRIX_RESIST(P_M)
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LOAD_MATRIX_RESIST(M_P)
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LOAD_MATRIX_RESIST(M_M)
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}
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#define LOAD_MATRIX_REACT(name) \
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*inst->jacobian_ptr_react[name] += inst->jacobian_react[name] * alpha;
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// implementation of the load_matrix_react function as defined in the OSDI spec
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void load_jacobian_react(void *inst_, double alpha)
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{
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CapacitorInstance *inst = (CapacitorInstance *)inst_;
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LOAD_MATRIX_REACT(P_P)
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LOAD_MATRIX_REACT(M_M)
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LOAD_MATRIX_REACT(P_M)
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LOAD_MATRIX_REACT(M_P)
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}
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#define LOAD_MATRIX_TRAN(name) \
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*inst->jacobian_ptr_resist[name] += inst->jacobian_react[name] * alpha;
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// implementation of the load_matrix_tran function as defined in the OSDI spec
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void load_jacobian_tran(void *inst_, double alpha)
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{
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CapacitorInstance *inst = (CapacitorInstance *)inst_;
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// set dc stamps
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load_jacobian_resist(inst_);
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// add reactive contributions
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LOAD_MATRIX_TRAN(P_P)
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LOAD_MATRIX_TRAN(M_M)
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LOAD_MATRIX_TRAN(M_P)
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LOAD_MATRIX_TRAN(M_M)
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}
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// implementation of the load_spice_rhs_dc function as defined in the OSDI spec
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void load_spice_rhs_dc(void *inst_, double *dst, double *prev_solve)
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{
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CapacitorInstance *inst = (CapacitorInstance *)inst_;
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double vp = prev_solve[inst->node_off[P]];
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double vm = prev_solve[inst->node_off[M]];
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dst[inst->node_off[P]] += inst->jacobian_resist[P_M] * vm +
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inst->jacobian_resist[P_P] * vp -
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inst->rhs_resist[P];
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dst[inst->node_off[M]] += inst->jacobian_resist[M_P] * vp +
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inst->jacobian_resist[M_M] * vm -
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inst->rhs_resist[M];
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}
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// implementation of the load_spice_rhs_tran function as defined in the OSDI
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// spec
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void load_spice_rhs_tran(void *inst_, double *dst, double *prev_solve,
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double alpha)
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{
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CapacitorInstance *inst = (CapacitorInstance *)inst_;
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double vp = prev_solve[inst->node_off[P]];
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double vm = prev_solve[inst->node_off[M]];
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// set DC rhs
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load_spice_rhs_dc(inst_, dst, prev_solve);
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// add contributions due to reactive elements
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dst[inst->node_off[P]] +=
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alpha * (inst->jacobian_react[P_P] * vp +
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inst->jacobian_react[P_M] * vm);
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dst[inst->node_off[M]] += alpha * (inst->jacobian_react[M_M] * vm +
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inst->jacobian_react[M_P] * vp);
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}
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// structure that provides information of all nodes of the model
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OsdiNode nodes[NUM_NODES] = {
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{.name = "P", .units = "V", .is_reactive = true},
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{.name = "M", .units = "V", .is_reactive = true},
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};
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// boolean array that tells which Jacobian entries are constant. Nothing is
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// constant with selfheating, though.
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bool const_jacobian_entries[NUM_MATRIX] = {};
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// these node pairs specify which entries in the Jacobian must be accounted for
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OsdiNodePair jacobian_entries[NUM_MATRIX] = {
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{P, P},
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{P, M},
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{M, P},
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{M, M},
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};
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#define NUM_PARAMS 1
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// the model parameters as defined in Verilog-A, bounds and default values are
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// stored elsewhere as they may depend on model parameters etc.
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OsdiParamOpvar params[NUM_PARAMS] = {
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{
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.name = (char *[]){"C"},
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.num_alias = 0,
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.description = "Capacitance",
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.units = "Farad",
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.flags = PARA_TY_REAL | PARA_KIND_MODEL,
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.len = 0,
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},
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};
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// fill exported data
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uint32_t OSDI_VERSION_MAJOR = OSDI_VERSION_MAJOR_CURR;
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uint32_t OSDI_VERSION_MINOR = OSDI_VERSION_MINOR_CURR;
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uint32_t OSDI_NUM_DESCRIPTORS = 1;
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// this is the main structure used by simulators, it gives access to all
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// information in a model
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OsdiDescriptor OSDI_DESCRIPTORS[1] = {{
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// metadata
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.name = "capacitor_va",
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// nodes
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.num_nodes = NUM_NODES,
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.num_terminals = 2,
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.nodes = (OsdiNode *)&nodes,
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// matrix entries
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.num_jacobian_entries = NUM_MATRIX,
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.jacobian_entries = (OsdiNodePair *)&jacobian_entries,
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.const_jacobian_entries = (bool *)&const_jacobian_entries,
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// memory
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.instance_size = sizeof(CapacitorInstance),
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.model_size = sizeof(CapacitorModel),
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.residual_resist_offset = offsetof(CapacitorInstance, rhs_resist),
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.residual_react_offset = offsetof(CapacitorInstance, rhs_react),
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.node_mapping_offset = offsetof(CapacitorInstance, node_off),
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.jacobian_resist_offset = offsetof(CapacitorInstance, jacobian_resist),
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.jacobian_react_offset = offsetof(CapacitorInstance, jacobian_react),
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.jacobian_ptr_resist_offset = offsetof(CapacitorInstance, jacobian_ptr_resist),
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.jacobian_ptr_react_offset = offsetof(CapacitorInstance, jacobian_ptr_react),
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// TODO add node collapsing to example
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// node collapsing
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.num_collapsible = 0,
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.collapsible = NULL,
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.is_collapsible_offset = 0,
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// noise
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.noise_sources = NULL,
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.num_noise_src = 0,
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// parameters and op vars
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.num_params = NUM_PARAMS,
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.num_instance_params = 0,
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.num_opvars = 0,
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.param_opvar = (OsdiParamOpvar *)¶ms,
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// setup
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.access = &osdi_access,
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.setup_model = &setup_model,
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.setup_instance = &setup_instance,
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.eval = &eval,
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.load_noise = &load_noise,
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.load_residual_resist = &load_residual_resist,
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.load_residual_react = &load_residual_react,
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.load_spice_rhs_dc = &load_spice_rhs_dc,
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.load_spice_rhs_tran = &load_spice_rhs_tran,
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.load_jacobian_resist = &load_jacobian_resist,
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.load_jacobian_react = &load_jacobian_react,
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.load_jacobian_tran = &load_jacobian_tran,
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}};
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@ -7,7 +7,7 @@ VD Dx 0 DC 0 AC 1 SIN (0.5 0.2 1M)
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Vsense Dx D DC 0
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* model definitions:
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.model cmod_osdi osdi capacitor_va c=5e-12
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.model cmod_osdi capacitor_va c=5e-12
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*OSDI Capacitor:
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*OSDI_ACTIVATE*A1 D 0 cmod_osdi
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@ -17,6 +17,7 @@ Vsense Dx D DC 0
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.control
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pre_osdi capacitor.osdi
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set filetype=ascii
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set wr_vecnames
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set wr_singlescale
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@ -2,10 +2,12 @@
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"""
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import os, shutil
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import numpy as np
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import subprocess
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import pandas as pd
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import sys
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sys.path.append(
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os.path.abspath(os.path.join(os.path.dirname(__file__), os.path.pardir)))
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directory = os.path.dirname(__file__)
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from testing import prepare_test
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# This test runs a DC, AC and Transient Simulation of a simple capacitor.
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# The capacitor is available as a C file and needs to be compiled to a shared object
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@ -17,78 +19,12 @@ directory = os.path.dirname(__file__)
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# The integration test proves the functioning of the OSDI interface.
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# Future tests will target Verilog-A models like HICUM/L2 that should yield exactly the same results as the Ngspice implementation.
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def create_shared_object():
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# place the file "capacitor_va.c" next to this file
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subprocess.run(
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[
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"gcc",
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"-c",
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"-Wall",
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"-I",
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"../../src/spicelib/devices/osdi/",
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"-fpic",
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"capacitor_va.c",
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"-ggdb",
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],
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cwd=directory,
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)
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subprocess.run(
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["gcc", "-shared", "-o", "capacitor_va.so", "capacitor_va.o", "-ggdb"],
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cwd=directory,
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)
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os.makedirs(os.path.join(directory, "test_osdi", "osdi"), exist_ok=True)
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subprocess.run(
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["mv", "capacitor_va.so", "test_osdi/osdi/capacitor_va.so"], cwd=directory
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)
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subprocess.run(["rm", "capacitor_va.o"], cwd=directory)
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# specify location of Ngspice executable to be tested
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ngspice_path = os.path.join(directory, "../../debug/src/ngspice")
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ngspice_path = os.path.abspath(ngspice_path)
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directory = os.path.dirname(__file__)
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def test_ngspice():
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path_netlist = os.path.join(directory, "netlist.sp")
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# open netlist and activate Ngspice capacitor
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with open(path_netlist) as netlist_handle:
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netlist_raw = netlist_handle.read()
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netlist_osdi = netlist_raw.replace("*OSDI_ACTIVATE*", "")
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netlist_built_in = netlist_raw.replace("*BUILT_IN_ACTIVATE*", "")
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# make directories for test cases
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dir_osdi = os.path.join(directory, "test_osdi")
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dir_built_in = os.path.join(directory, "test_built_in")
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# remove old results:
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for directory_i in [dir_osdi, dir_built_in]:
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shutil.rmtree(directory_i, ignore_errors=True)
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for directory_i in [dir_osdi, dir_built_in]:
|
||||
os.makedirs(directory_i, exist_ok=True)
|
||||
|
||||
create_shared_object()
|
||||
|
||||
# write netlists
|
||||
with open(os.path.join(dir_osdi, "netlist.sp"), "w") as netlist_handle:
|
||||
netlist_handle.write(netlist_osdi)
|
||||
|
||||
with open(os.path.join(dir_built_in, "netlist.sp"), "w") as netlist_handle:
|
||||
netlist_handle.write(netlist_built_in)
|
||||
|
||||
# run simulations with Ngspice
|
||||
for directory_i in [dir_osdi, dir_built_in]:
|
||||
subprocess.run(
|
||||
[
|
||||
ngspice_path,
|
||||
"netlist.sp",
|
||||
"-b",
|
||||
],
|
||||
cwd=directory_i,
|
||||
)
|
||||
|
||||
dir_osdi, dir_built_in = prepare_test(directory)
|
||||
|
||||
# read DC simulation results
|
||||
dc_data_osdi = pd.read_csv(os.path.join(dir_osdi, "dc_sim.ngspice"), sep="\\s+")
|
||||
dc_data_built_in = pd.read_csv(os.path.join(dir_osdi, "dc_sim.ngspice"), sep="\\s+")
|
||||
|
|
|
|||
|
|
@ -2,10 +2,12 @@
|
|||
"""
|
||||
import os, shutil
|
||||
import numpy as np
|
||||
import subprocess
|
||||
import pandas as pd
|
||||
import sys
|
||||
sys.path.append(
|
||||
os.path.abspath(os.path.join(os.path.dirname(__file__), os.path.pardir)))
|
||||
|
||||
directory = os.path.dirname(__file__)
|
||||
from testing import prepare_test
|
||||
|
||||
# This test runs a DC, AC and Transient Simulation of a simple diode.
|
||||
# The diode is available in the "OSDI" Git project and needs to be compiled to a shared object
|
||||
|
|
@ -18,74 +20,11 @@ directory = os.path.dirname(__file__)
|
|||
# complicated and the results are therefore not exactly the same.
|
||||
# Future tests will target Verilog-A models like HICUM/L2 that should yield exactly the same results as the Ngspice implementation.
|
||||
|
||||
|
||||
def create_shared_object():
|
||||
# place the file "diode.c" next to this file
|
||||
subprocess.run(
|
||||
[
|
||||
"gcc",
|
||||
"-c",
|
||||
"-Wall",
|
||||
"-I",
|
||||
"../../src/osdi/",
|
||||
"-fpic",
|
||||
"diode.c",
|
||||
"-ggdb",
|
||||
],
|
||||
cwd=directory,
|
||||
)
|
||||
subprocess.run(
|
||||
["gcc", "-shared", "-o", "diode.osdi", "diode.o", "-ggdb"],
|
||||
cwd=directory,
|
||||
)
|
||||
subprocess.run(["mv", "diode.osdi", "test_osdi/diode.osdi"], cwd=directory)
|
||||
subprocess.run(["rm", "diode.o"], cwd=directory)
|
||||
|
||||
|
||||
# specify location of Ngspice executable to be tested
|
||||
ngspice_path = os.path.join(directory, "../../debug/src/ngspice")
|
||||
ngspice_path = os.path.abspath(ngspice_path)
|
||||
directory = os.path.dirname(__file__)
|
||||
|
||||
|
||||
def test_ngspice():
|
||||
path_netlist = os.path.join(directory, "netlist.sp")
|
||||
|
||||
# open netlist and activate Ngspice diode
|
||||
with open(path_netlist) as netlist_handle:
|
||||
netlist_raw = netlist_handle.read()
|
||||
|
||||
netlist_osdi = netlist_raw.replace("*OSDI_ACTIVATE*", "")
|
||||
netlist_built_in = netlist_raw.replace("*BUILT_IN_ACTIVATE*", "")
|
||||
|
||||
# make directories for test cases
|
||||
dir_osdi = os.path.join(directory, "test_osdi")
|
||||
dir_built_in = os.path.join(directory, "test_built_in")
|
||||
# remove old results:
|
||||
for directory_i in [dir_osdi, dir_built_in]:
|
||||
shutil.rmtree(directory_i, ignore_errors=True)
|
||||
|
||||
for directory_i in [dir_osdi, dir_built_in]:
|
||||
os.makedirs(directory_i, exist_ok=True)
|
||||
|
||||
create_shared_object()
|
||||
|
||||
# write netlists
|
||||
with open(os.path.join(dir_osdi, "netlist.sp"), "w") as netlist_handle:
|
||||
netlist_handle.write(netlist_osdi)
|
||||
|
||||
with open(os.path.join(dir_built_in, "netlist.sp"), "w") as netlist_handle:
|
||||
netlist_handle.write(netlist_built_in)
|
||||
|
||||
# run simulations with Ngspice
|
||||
for directory_i in [dir_osdi, dir_built_in]:
|
||||
subprocess.run(
|
||||
[
|
||||
ngspice_path,
|
||||
"netlist.sp",
|
||||
"-b",
|
||||
],
|
||||
cwd=directory_i,
|
||||
)
|
||||
dir_osdi, dir_built_in = prepare_test(directory)
|
||||
|
||||
# read DC simulation results
|
||||
dc_data_osdi = pd.read_csv(os.path.join(dir_osdi, "dc_sim.ngspice"), sep="\\s+")
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -1,4 +1,4 @@
|
|||
OSDI Resistor Test
|
||||
OSDI Multiple Devices Test
|
||||
.options abstol=1e-15
|
||||
|
||||
|
||||
|
|
@ -7,15 +7,17 @@ VD Dx 0 DC 0 AC 1 SIN (0.5 0.2 1M)
|
|||
Vsense Dx D DC 0
|
||||
|
||||
* model definitions:
|
||||
.model rmod_osdi resistor_va r=10
|
||||
.model rmod_osdi resistor_va r=20
|
||||
.model cmod_osdi capacitor_va r=5e-12
|
||||
|
||||
*OSDI Resistor and Capacitor:
|
||||
*OSDI_ACTIVATE*A1 D 0 rmod_osdi
|
||||
*OSDI_ACTIVATE*A2 D 0 cmod_osdi
|
||||
*OSDI_ACTIVATE*A2 D 0 rmod_osdi
|
||||
*OSDI_ACTIVATE*A3 D 0 cmod_osdi
|
||||
|
||||
*Built-in Capacitor and Resistor:
|
||||
*BUILT_IN_ACTIVATE*R1 D 0 10
|
||||
*BUILT_IN_ACTIVATE*R1 D 0 20
|
||||
*BUILT_IN_ACTIVATE*R2 D 0 20
|
||||
*BUILT_IN_ACTIVATE*C1 D 0 5e-12
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -2,10 +2,12 @@
|
|||
"""
|
||||
import os, shutil
|
||||
import numpy as np
|
||||
import subprocess
|
||||
import pandas as pd
|
||||
import sys
|
||||
sys.path.append(
|
||||
os.path.abspath(os.path.join(os.path.dirname(__file__), os.path.pardir)))
|
||||
|
||||
directory = os.path.dirname(__file__)
|
||||
from testing import prepare_test
|
||||
|
||||
# This test runs a DC, AC and Transient Simulation of a simple resistor and resistor.
|
||||
# The capacitor and resistor are available as C files and need to be compiled to a shared objects
|
||||
|
|
@ -20,101 +22,31 @@ directory = os.path.dirname(__file__)
|
|||
# Future tests will target Verilog-A models like HICUM/L2 that should yield exactly the same results as the Ngspice implementation.
|
||||
|
||||
|
||||
def create_shared_object():
|
||||
# place the file "resistor.c" and "capacitor.c" next to this file
|
||||
for dev in ["capacitor", "resistor"]:
|
||||
subprocess.run(
|
||||
[
|
||||
"gcc",
|
||||
"-c",
|
||||
"-Wall",
|
||||
"-I",
|
||||
"../../src/osdi/",
|
||||
"-fpic",
|
||||
dev + ".c",
|
||||
"-ggdb",
|
||||
],
|
||||
cwd=directory,
|
||||
)
|
||||
subprocess.run(
|
||||
["gcc", "-shared", "-o", dev + ".osdi", dev + ".o", "-ggdb"],
|
||||
cwd=directory,
|
||||
)
|
||||
subprocess.run(
|
||||
["mv", dev + ".osdi", "test_osdi/" + dev + ".osdi"], cwd=directory
|
||||
)
|
||||
subprocess.run(["rm", dev + ".o"], cwd=directory)
|
||||
|
||||
|
||||
# specify location of Ngspice executable to be tested
|
||||
ngspice_path = os.path.join(directory, "../../debug/src/ngspice")
|
||||
ngspice_path = os.path.abspath(ngspice_path)
|
||||
|
||||
directory = os.path.dirname(__file__)
|
||||
|
||||
def test_ngspice():
|
||||
path_netlist = os.path.join(directory, "netlist.sp")
|
||||
|
||||
# open netlist and activate Ngspice devices
|
||||
with open(path_netlist) as netlist_handle:
|
||||
netlist_raw = netlist_handle.read()
|
||||
|
||||
netlist_osdi = netlist_raw.replace("*OSDI_ACTIVATE*", "")
|
||||
netlist_built_in = netlist_raw.replace("*BUILT_IN_ACTIVATE*", "")
|
||||
|
||||
# make directories for test cases
|
||||
dir_osdi = os.path.join(directory, "test_osdi")
|
||||
dir_built_in = os.path.join(directory, "test_built_in")
|
||||
# remove old results:
|
||||
for directory_i in [dir_osdi, dir_built_in]:
|
||||
shutil.rmtree(directory_i, ignore_errors=True)
|
||||
|
||||
for directory_i in [dir_osdi, dir_built_in]:
|
||||
os.makedirs(directory_i, exist_ok=True)
|
||||
|
||||
create_shared_object()
|
||||
|
||||
# write netlists
|
||||
with open(os.path.join(dir_osdi, "netlist.sp"), "w") as netlist_handle:
|
||||
netlist_handle.write(netlist_osdi)
|
||||
|
||||
with open(os.path.join(dir_built_in, "netlist.sp"), "w") as netlist_handle:
|
||||
netlist_handle.write(netlist_built_in)
|
||||
|
||||
# run simulations with Ngspice
|
||||
for directory_i in [dir_osdi, dir_built_in]:
|
||||
subprocess.run(
|
||||
[
|
||||
ngspice_path,
|
||||
"netlist.sp",
|
||||
"-b",
|
||||
],
|
||||
cwd=directory_i,
|
||||
)
|
||||
dir_osdi, dir_built_in = prepare_test(directory)
|
||||
|
||||
# read DC simulation results
|
||||
dc_data_osdi = pd.read_csv(os.path.join(dir_osdi, "dc_sim.ngspice"), sep="\\s+")
|
||||
dc_data_built_in = pd.read_csv(os.path.join(dir_osdi, "dc_sim.ngspice"), sep="\\s+")
|
||||
# dc_data_built_in = pd.read_csv(
|
||||
# os.path.join(dir_built_in, "dc_sim.ngspice"), sep="\\s+"
|
||||
# )
|
||||
dc_data_built_in = pd.read_csv(
|
||||
os.path.join(dir_built_in, "dc_sim.ngspice"), sep="\\s+"
|
||||
)
|
||||
|
||||
id_osdi = dc_data_osdi["i(vsense)"].to_numpy()
|
||||
id_built_in = dc_data_osdi["i(vsense)"].to_numpy()
|
||||
# id_built_in = dc_data_built_in["i(vsense)"].to_numpy()
|
||||
id_built_in = dc_data_built_in["i(vsense)"].to_numpy()
|
||||
|
||||
# read AC simulation results
|
||||
ac_data_osdi = pd.read_csv(os.path.join(dir_osdi, "ac_sim.ngspice"), sep="\\s+")
|
||||
ac_data_built_in = pd.read_csv(os.path.join(dir_osdi, "ac_sim.ngspice"), sep="\\s+")
|
||||
# ac_data_built_in = pd.read_csv(
|
||||
# os.path.join(dir_built_in, "ac_sim.ngspice"), sep="\\s+"
|
||||
# )
|
||||
ac_data_built_in = pd.read_csv(
|
||||
os.path.join(dir_built_in, "ac_sim.ngspice"), sep="\\s+"
|
||||
)
|
||||
|
||||
# read TR simulation results
|
||||
tr_data_osdi = pd.read_csv(os.path.join(dir_osdi, "tr_sim.ngspice"), sep="\\s+")
|
||||
tr_data_built_in = pd.read_csv(os.path.join(dir_osdi, "tr_sim.ngspice"), sep="\\s+")
|
||||
# tr_data_built_in = pd.read_csv(
|
||||
# os.path.join(dir_built_in, "tr_sim.ngspice"), sep="\\s+"
|
||||
# )
|
||||
tr_data_built_in = pd.read_csv(
|
||||
os.path.join(dir_built_in, "tr_sim.ngspice"), sep="\\s+"
|
||||
)
|
||||
|
||||
# test simulation results
|
||||
id_osdi = dc_data_osdi["i(vsense)"].to_numpy()
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ VD Dx 0 DC 0 AC 1 SIN (0.5 0.2 1M)
|
|||
Vsense Dx D DC 0
|
||||
|
||||
* model definitions:
|
||||
.model rmod_osdi osdi resistor_va r=10
|
||||
.model rmod_osdi resistor_va r=10
|
||||
|
||||
*OSDI Resistor:
|
||||
*OSDI_ACTIVATE*A1 D 0 rmod_osdi
|
||||
|
|
@ -17,6 +17,8 @@ Vsense Dx D DC 0
|
|||
|
||||
|
||||
.control
|
||||
pre_osdi resistor.osdi
|
||||
|
||||
set filetype=ascii
|
||||
set wr_vecnames
|
||||
set wr_singlescale
|
||||
|
|
|
|||
|
|
@ -5,7 +5,12 @@ import numpy as np
|
|||
import subprocess
|
||||
import pandas as pd
|
||||
|
||||
directory = os.path.dirname(__file__)
|
||||
import sys
|
||||
sys.path.append(
|
||||
os.path.abspath(os.path.join(os.path.dirname(__file__), os.path.pardir)))
|
||||
|
||||
from testing import prepare_test
|
||||
|
||||
|
||||
# This test runs a DC, AC and Transient Simulation of a simple resistor.
|
||||
# The capacitor is available as a C file and needs to be compiled to a shared object
|
||||
|
|
@ -17,102 +22,32 @@ directory = os.path.dirname(__file__)
|
|||
# The integration test proves the functioning of the OSDI interface.
|
||||
# Future tests will target Verilog-A models like HICUM/L2 that should yield exactly the same results as the Ngspice implementation.
|
||||
|
||||
|
||||
def create_shared_object():
|
||||
# place the file "resistor_va.c" next to this file
|
||||
subprocess.run(
|
||||
[
|
||||
"gcc",
|
||||
"-c",
|
||||
"-Wall",
|
||||
"-I",
|
||||
"../../src/spicelib/devices/osdi/",
|
||||
"-fpic",
|
||||
"resistor_va.c",
|
||||
"-ggdb",
|
||||
],
|
||||
cwd=directory,
|
||||
)
|
||||
subprocess.run(
|
||||
["gcc", "-shared", "-o", "resistor_va.so", "resistor_va.o", "-ggdb"],
|
||||
cwd=directory,
|
||||
)
|
||||
os.makedirs(os.path.join(directory, "test_osdi", "osdi"), exist_ok=True)
|
||||
subprocess.run(
|
||||
["mv", "resistor_va.so", "test_osdi/osdi/resistor_va.so"], cwd=directory
|
||||
)
|
||||
subprocess.run(["rm", "resistor_va.o"], cwd=directory)
|
||||
|
||||
|
||||
# specify location of Ngspice executable to be tested
|
||||
ngspice_path = os.path.join(directory, "../../debug/src/ngspice")
|
||||
ngspice_path = os.path.abspath(ngspice_path)
|
||||
directory = os.path.dirname(__file__)
|
||||
|
||||
|
||||
def test_ngspice():
|
||||
path_netlist = os.path.join(directory, "netlist.sp")
|
||||
|
||||
# open netlist and activate Ngspice resistor
|
||||
with open(path_netlist) as netlist_handle:
|
||||
netlist_raw = netlist_handle.read()
|
||||
|
||||
netlist_osdi = netlist_raw.replace("*OSDI_ACTIVATE*", "")
|
||||
netlist_built_in = netlist_raw.replace("*BUILT_IN_ACTIVATE*", "")
|
||||
|
||||
# make directories for test cases
|
||||
dir_osdi = os.path.join(directory, "test_osdi")
|
||||
dir_built_in = os.path.join(directory, "test_built_in")
|
||||
# remove old results:
|
||||
for directory_i in [dir_osdi, dir_built_in]:
|
||||
shutil.rmtree(directory_i, ignore_errors=True)
|
||||
|
||||
for directory_i in [dir_osdi, dir_built_in]:
|
||||
os.makedirs(directory_i, exist_ok=True)
|
||||
|
||||
create_shared_object()
|
||||
|
||||
# write netlists
|
||||
with open(os.path.join(dir_osdi, "netlist.sp"), "w") as netlist_handle:
|
||||
netlist_handle.write(netlist_osdi)
|
||||
|
||||
with open(os.path.join(dir_built_in, "netlist.sp"), "w") as netlist_handle:
|
||||
netlist_handle.write(netlist_built_in)
|
||||
|
||||
# run simulations with Ngspice
|
||||
for directory_i in [dir_osdi, dir_built_in]:
|
||||
subprocess.run(
|
||||
[
|
||||
ngspice_path,
|
||||
"netlist.sp",
|
||||
"-b",
|
||||
],
|
||||
cwd=directory_i,
|
||||
)
|
||||
dir_osdi, dir_built_in = prepare_test(directory)
|
||||
|
||||
# read DC simulation results
|
||||
dc_data_osdi = pd.read_csv(os.path.join(dir_osdi, "dc_sim.ngspice"), sep="\\s+")
|
||||
dc_data_built_in = pd.read_csv(os.path.join(dir_osdi, "dc_sim.ngspice"), sep="\\s+")
|
||||
# dc_data_built_in = pd.read_csv(
|
||||
# os.path.join(dir_built_in, "dc_sim.ngspice"), sep="\\s+"
|
||||
# )
|
||||
dc_data_built_in = pd.read_csv(
|
||||
os.path.join(dir_built_in, "dc_sim.ngspice"), sep="\\s+"
|
||||
)
|
||||
|
||||
id_osdi = dc_data_osdi["i(vsense)"].to_numpy()
|
||||
id_built_in = dc_data_osdi["i(vsense)"].to_numpy()
|
||||
# id_built_in = dc_data_built_in["i(vsense)"].to_numpy()
|
||||
id_built_in = dc_data_built_in["i(vsense)"].to_numpy()
|
||||
|
||||
# read AC simulation results
|
||||
ac_data_osdi = pd.read_csv(os.path.join(dir_osdi, "ac_sim.ngspice"), sep="\\s+")
|
||||
ac_data_built_in = pd.read_csv(os.path.join(dir_osdi, "ac_sim.ngspice"), sep="\\s+")
|
||||
# ac_data_built_in = pd.read_csv(
|
||||
# os.path.join(dir_built_in, "ac_sim.ngspice"), sep="\\s+"
|
||||
# )
|
||||
ac_data_built_in = pd.read_csv(
|
||||
os.path.join(dir_built_in, "ac_sim.ngspice"), sep="\\s+"
|
||||
)
|
||||
|
||||
# read TR simulation results
|
||||
tr_data_osdi = pd.read_csv(os.path.join(dir_osdi, "tr_sim.ngspice"), sep="\\s+")
|
||||
tr_data_built_in = pd.read_csv(os.path.join(dir_osdi, "tr_sim.ngspice"), sep="\\s+")
|
||||
# tr_data_built_in = pd.read_csv(
|
||||
# os.path.join(dir_built_in, "tr_sim.ngspice"), sep="\\s+"
|
||||
# )
|
||||
tr_data_built_in = pd.read_csv(
|
||||
os.path.join(dir_built_in, "tr_sim.ngspice"), sep="\\s+"
|
||||
)
|
||||
|
||||
# test simulation results
|
||||
id_osdi = dc_data_osdi["i(vsense)"].to_numpy()
|
||||
|
|
|
|||
|
|
@ -0,0 +1,94 @@
|
|||
#this file defines some common routines used by the OSDI test cases
|
||||
import subprocess
|
||||
import os
|
||||
import shutil
|
||||
import glob
|
||||
from pathlib import Path
|
||||
|
||||
# specify location of Ngspice executable to be tested
|
||||
directory_testing = os.path.dirname(__file__)
|
||||
ngspice_path = os.path.join(directory_testing, "../debug/src/ngspice")
|
||||
ngspice_path = os.path.abspath(ngspice_path)
|
||||
|
||||
def create_shared_objects(directory):
|
||||
c_files = []
|
||||
for c_file in glob.glob(directory + "/*.c"):
|
||||
basename = Path(c_file).stem
|
||||
c_files.append(basename)
|
||||
|
||||
for c_file in c_files:
|
||||
subprocess.run(
|
||||
[
|
||||
"gcc",
|
||||
"-c",
|
||||
"-Wall",
|
||||
"-I",
|
||||
"../../src/osdi/",
|
||||
"-fpic",
|
||||
c_file + ".c",
|
||||
"-ggdb",
|
||||
],
|
||||
cwd=directory,
|
||||
)
|
||||
subprocess.run(
|
||||
["gcc", "-shared", "-o", c_file + ".osdi", c_file + ".o", "-ggdb"],
|
||||
cwd=directory,
|
||||
)
|
||||
subprocess.run(
|
||||
["mv", c_file + ".osdi", "test_osdi/" + c_file + ".osdi"], cwd=directory
|
||||
)
|
||||
subprocess.run(["rm", c_file + ".o"], cwd=directory)
|
||||
|
||||
def prepare_dirs(directory):
|
||||
# directories for test cases
|
||||
dir_osdi = os.path.join(directory, "test_osdi")
|
||||
dir_built_in = os.path.join(directory, "test_built_in")
|
||||
|
||||
for directory_i in [dir_osdi, dir_built_in]:
|
||||
# remove old results
|
||||
shutil.rmtree(directory_i, ignore_errors=True)
|
||||
# make new directories
|
||||
os.makedirs(directory_i, exist_ok=True)
|
||||
|
||||
|
||||
return dir_osdi, dir_built_in
|
||||
|
||||
def prepare_netlists(directory):
|
||||
path_netlist = os.path.join(directory, "netlist.sp")
|
||||
|
||||
# directories for test cases
|
||||
dir_osdi = os.path.join(directory, "test_osdi")
|
||||
dir_built_in = os.path.join(directory, "test_built_in")
|
||||
|
||||
# open netlist and activate Ngspice devices
|
||||
with open(path_netlist) as netlist_handle:
|
||||
netlist_raw = netlist_handle.read()
|
||||
|
||||
netlist_osdi = netlist_raw.replace("*OSDI_ACTIVATE*", "")
|
||||
netlist_built_in = netlist_raw.replace("*BUILT_IN_ACTIVATE*", "")
|
||||
|
||||
# write netlists
|
||||
with open(os.path.join(dir_osdi, "netlist.sp"), "w") as netlist_handle:
|
||||
netlist_handle.write(netlist_osdi)
|
||||
|
||||
with open(os.path.join(dir_built_in, "netlist.sp"), "w") as netlist_handle:
|
||||
netlist_handle.write(netlist_built_in)
|
||||
|
||||
def run_simulations(dirs):
|
||||
for dir_i in dirs:
|
||||
subprocess.run(
|
||||
[
|
||||
ngspice_path,
|
||||
"netlist.sp",
|
||||
"-b",
|
||||
],
|
||||
cwd=dir_i,
|
||||
)
|
||||
|
||||
def prepare_test(directory):
|
||||
dir_osdi, dir_built_in = prepare_dirs(directory)
|
||||
create_shared_objects(directory)
|
||||
prepare_netlists(directory)
|
||||
run_simulations([dir_osdi, dir_built_in])
|
||||
|
||||
return dir_osdi, dir_built_in
|
||||
Loading…
Reference in New Issue