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bsimcmg, edit benchmark_test files for first ngspice experiments 

FIXME and beware,
  parameter LSP has a different default !
This commit is contained in:
rlar 2017-07-07 19:49:08 +02:00
parent ce13f713a6
commit 928606f815
14 changed files with 95 additions and 29 deletions
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12
bsimcmg_benchmark_test/ac.sp
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@ -1,9 +1,10 @@
*Sample netlist for BSIM-MG *Sample netlist for BSIM-MG
* (exec-spice "ngspice %s" t)
*AC Response *AC Response
.option abstol=1e-6 reltol=1e-6 post ingold .option abstol=1e-6 reltol=1e-6 post ingold
.hdl "bsimcmg.va" *.hdl "bsimcmg.va"
.include "modelcard.nmos" .include "modelcard.nmos"
.param myvdd=1.0 .param myvdd=1.0
@ -14,7 +15,7 @@ vsig gate 0 dc=0.5 ac=1
vbs bulk 0 dc=0 vbs bulk 0 dc=0
* --- Transistor --- * --- Transistor ---
X1 vout gate 0 bulk nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1 m1 vout gate 0 bulk 0 nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
* --- Load --- * --- Load ---
rl supply vout r=2k rl supply vout r=2k
@ -31,5 +32,12 @@ cl supply vout c=10f
*.alter *.alter
*.param myvdd=2.0 *.param myvdd=2.0
.control
run
plot vdb(vout)
plot cph(vout)
.endc
.end .end

9
bsimcmg_benchmark_test/gummel_n.sp
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@ -1,9 +1,9 @@
*Sample netlist for BSIM-MG *Sample netlist for BSIM-MG
* (exec-spice "ngspice %s" t)
*Drain current symmetry for nmos *Drain current symmetry for nmos
.option abstol=1e-6 reltol=1e-6 post ingold .option abstol=1e-6 reltol=1e-6 post ingold
.hdl "bsimcmg.va"
.include "modelcard.nmos" .include "modelcard.nmos"
* --- Voltage Sources --- * --- Voltage Sources ---
@ -14,7 +14,7 @@ vbulk bulk 0 dc=0.0
* --- Transistor --- * --- Transistor ---
X1 drain gate source bulk nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1 m1 drain gate source bulk 0 nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
* --- DC Analysis --- * --- DC Analysis ---
.dc vdrain -0.1 0.1 0.001 vgate 0.0 1.0 0.2 .dc vdrain -0.1 0.1 0.001 vgate 0.0 1.0 0.2
@ -25,4 +25,9 @@ X1 drain gate source bulk nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
.probe dc gx4=deriv(gx3) .probe dc gx4=deriv(gx3)
.print dc par'ids' par'gx' par'gx2' par'gx3' par 'gx4' .print dc par'ids' par'gx' par'gx2' par'gx3' par 'gx4'
.control
run
plot -i(vdrain)
.endc
.end .end

10
bsimcmg_benchmark_test/gummel_p.sp
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@ -1,9 +1,10 @@
*Sample netlist for BSIM-MG *Sample netlist for BSIM-MG
* (exec-spice "ngspice %s" t)
*Drain current symmetry *Drain current symmetry
.option abstol=1e-6 reltol=1e-6 post ingold .option abstol=1e-6 reltol=1e-6 post ingold
.hdl "bsimcmg.va" *.hdl "bsimcmg.va"
.include "modelcard.pmos" .include "modelcard.pmos"
* --- Voltage Sources --- * --- Voltage Sources ---
@ -14,7 +15,7 @@ vbulk bulk 0 dc=0
* --- Transistor --- * --- Transistor ---
X1 drain gate source bulk pmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1 m1 drain gate source bulk 0 pmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
* --- DC Analysis --- * --- DC Analysis ---
.dc vdrain -0.1 0.1 0.001 vgate 0.0 -1.0 -0.2 .dc vdrain -0.1 0.1 0.001 vgate 0.0 -1.0 -0.2
@ -25,4 +26,9 @@ X1 drain gate source bulk pmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
.probe dc gx4=deriv(gx3) .probe dc gx4=deriv(gx3)
.print dc par'ids' par'gx' par'gx2' par'gx3' par 'gx4' .print dc par'ids' par'gx' par'gx2' par'gx3' par 'gx4'
.control
run
plot -i(vdrain)
.endc
.end .end

11
bsimcmg_benchmark_test/idvdnmos.sp
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@ -1,10 +1,11 @@
*Sample netlist for BSIM-MG *Sample netlist for BSIM-MG
* (exec-spice "ngspice %s" t)
*Id-Vd Characteristics for NMOS (T = 27 C) *Id-Vd Characteristics for NMOS (T = 27 C)
.option abstol=1e-6 reltol=1e-6 post ingold .option abstol=1e-6 reltol=1e-6 post ingold
.temp -55 .temp -55
.hdl "bsimcmg.va" *.hdl "bsimcmg.va"
.include "modelcard.nmos.1" .include "modelcard.nmos.1"
* --- Voltage Sources --- * --- Voltage Sources ---
@ -13,7 +14,7 @@ vgs gate 0 dc=1.0
vbs bulk 0 dc=0.2 vbs bulk 0 dc=0.2
* --- Transistor --- * --- Transistor ---
X1 drain gate 0 bulk nmos1 TFIN=15n L=40n NFIN=10 NRS=1 NRD=1 m1 drain gate 0 bulk 0 nmos1 TFIN=15n L=40n NFIN=10 NRS=1 NRD=1
* --- DC Analysis --- * --- DC Analysis ---
.dc vds 0 1 0.01 vgs 0 1.0 0.1 .dc vds 0 1 0.01 vgs 0 1.0 0.1
@ -27,4 +28,10 @@ X1 drain gate 0 bulk nmos1 TFIN=15n L=40n NFIN=10 NRS=1 NRD=1
.alter .alter
.temp 100 .temp 100
.control
run
plot -i(vds)
* fixme, second temperature, and nasty reset issues
.endc
.end .end

11
bsimcmg_benchmark_test/idvdpmos.sp
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@ -1,10 +1,11 @@
*Sample netlist for BSIM-MG *Sample netlist for BSIM-MG
* (exec-spice "ngspice %s" t)
*Id-Vd Characteristics for PMOS (T = 27 C) *Id-Vd Characteristics for PMOS (T = 27 C)
.option abstol=1e-6 reltol=1e-6 post ingold .option abstol=1e-6 reltol=1e-6 post ingold
.temp -55 .temp -55
.hdl "bsimcmg.va" *.hdl "bsimcmg.va"
.include "modelcard.pmos.1" .include "modelcard.pmos.1"
* --- Voltage Sources --- * --- Voltage Sources ---
@ -13,7 +14,7 @@ vgs gate 0 dc=-1
vbs bulk 0 dc=0 vbs bulk 0 dc=0
* --- Transistor --- * --- Transistor ---
X1 drain gate 0 bulk pmos1 TFIN=15n L=40n NFIN=10 NRS=1 NRD=1 m1 drain gate 0 bulk 0 pmos1 TFIN=15n L=40n NFIN=10 NRS=1 NRD=1
* --- DC Analysis --- * --- DC Analysis ---
.dc vds 0 -1 -0.01 vgs 0 -1.0 -0.1 .dc vds 0 -1 -0.01 vgs 0 -1.0 -0.1
@ -27,4 +28,10 @@ X1 drain gate 0 bulk pmos1 TFIN=15n L=40n NFIN=10 NRS=1 NRD=1
.alter .alter
.temp 100 .temp 100
.control
run
plot i(vds)
* fixme, second temperature, and nasty reset issues
.endc
.end .end

12
bsimcmg_benchmark_test/idvgnmos.sp
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@ -1,10 +1,11 @@
*Sample netlist for BSIM-MG *Sample netlist for BSIM-MG
* (exec-spice "ngspice %s" t)
*Id-Vg Characteristics for NMOS (T = 27 C) *Id-Vg Characteristics for NMOS (T = 27 C)
.option abstol=1e-6 reltol=1e-6 post ingold .option abstol=1e-6 reltol=1e-6 post ingold
.temp 27 .temp 27
.hdl "bsimcmg.va" *.hdl "bsimcmg.va"
.include "modelcard.nmos.1" .include "modelcard.nmos.1"
* --- Voltage Sources --- * --- Voltage Sources ---
@ -14,7 +15,7 @@ vbs bulk 0 dc=0
vt t 0 dc= 0 vt t 0 dc= 0
* --- Transistor --- * --- Transistor ---
X1 supply gate 0 bulk t nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1 m1 supply gate 0 bulk t nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
* --- DC Analysis --- * --- DC Analysis ---
.dc vgs -0.5 1.0 0.01 vds 0.05 1 0.95 .dc vgs -0.5 1.0 0.01 vds 0.05 1 0.95
@ -28,4 +29,11 @@ X1 supply gate 0 bulk t nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
.alter .alter
.temp 100 .temp 100
.control
run
plot -i(vds)
plot -i(vbs)
* fixme, second temperature, and nasty reset issues
.endc
.end .end

11
bsimcmg_benchmark_test/idvgpmos.sp
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@ -1,10 +1,11 @@
*Sample netlist for BSIM-MG *Sample netlist for BSIM-MG
* (exec-spice "ngspice %s" t)
*Id-Vg Characteristics for PMOS (T = 27 C) *Id-Vg Characteristics for PMOS (T = 27 C)
.option abstol=1e-6 reltol=1e-6 post ingold .option abstol=1e-6 reltol=1e-6 post ingold
.temp -55 .temp -55
.hdl "bsimcmg.va" *.hdl "bsimcmg.va"
.include "modelcard.pmos.1" .include "modelcard.pmos.1"
* --- Voltage Sources --- * --- Voltage Sources ---
@ -13,7 +14,7 @@ vgs gate 0 dc=-1
vbs bulk 0 dc=0 vbs bulk 0 dc=0
* --- Transistor --- * --- Transistor ---
X1 supply gate 0 bulk pmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1 m1 supply gate 0 bulk 0 pmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
* --- DC Analysis --- * --- DC Analysis ---
.dc vgs 0.5 -1.0 -0.01 .dc vgs 0.5 -1.0 -0.01
@ -27,4 +28,10 @@ X1 supply gate 0 bulk pmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
.alter .alter
.temp 100 .temp 100
.control
run
plot i(vds)
* fixme, second temperature, and nasty reset issues
.endc
.end .end

12
bsimcmg_benchmark_test/invdc.sp
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@ -1,9 +1,10 @@
*Sample netlist for BSIM-MG *Sample netlist for BSIM-MG
* (exec-spice "ngspice %s" t)
*Inverter Transient *Inverter Transient
.option abstol=1e-6 reltol=1e-6 post ingold .option abstol=1e-6 reltol=1e-6 post ingold
.hdl "bsimcmg.va" *.hdl "bsimcmg.va"
.include "modelcard.nmos" .include "modelcard.nmos"
.include "modelcard.pmos" .include "modelcard.pmos"
@ -13,8 +14,8 @@ vin vi 0 dc=0.5
* --- Inverter Subcircuit --- * --- Inverter Subcircuit ---
.subckt mg_inv vin vout vdd gnd .subckt mg_inv vin vout vdd gnd
Xp1 vout vin vdd gnd pmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1 mp1 vout vin vdd gnd 0 pmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
Xn1 vout vin gnd gnd nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1 mn1 vout vin gnd gnd 0 nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
.ends .ends
* --- Inverter --- * --- Inverter ---
@ -25,4 +26,9 @@ Xinv1 vi vo supply 0 mg_inv
.print dc v(vi) v(vo) .print dc v(vi) v(vo)
.control
run
plot v(vi) v(vo)
.endc
.end .end

14
bsimcmg_benchmark_test/inverter_transient.sp
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@ -1,9 +1,10 @@
*Sample netlist for BSIM-MG *Sample netlist for BSIM-MG
* (exec-spice "ngspice %s" t)
*Inverter Transient *Inverter Transient
.option abstol=1e-6 reltol=1e-6 post ingold .option abstol=1e-6 reltol=1e-6 post ingold
.hdl "bsimcmg.va" *.hdl "bsimcmg.va"
.include "modelcard.nmos" .include "modelcard.nmos"
.include "modelcard.pmos" .include "modelcard.pmos"
@ -13,8 +14,8 @@ vsig vi 0 dc=0.5 sin (0.5 0.5 1MEG)
* --- Inverter Subcircuit --- * --- Inverter Subcircuit ---
.subckt mg_inv vin vout vdd gnd .subckt mg_inv vin vout vdd gnd
Xp1 vout vin vdd gnd pmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1 mp1 vout vin vdd gnd 0 pmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1
Xn1 vout vin gnd gnd nmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1 mn1 vout vin gnd gnd 0 nmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1
.ends .ends
* --- Inverter --- * --- Inverter ---
@ -25,8 +26,13 @@ Xinv4 3 4 supply 0 mg_inv
Xinv5 4 vo supply 0 mg_inv Xinv5 4 vo supply 0 mg_inv
* --- Transient Analysis --- * --- Transient Analysis ---
.tran 10n 5u .tran 20n 5u
.print tran v(vi) v(vo) .print tran v(vi) v(vo)
.control
run
plot v(vi) v(vo)
.endc
.end .end

2
bsimcmg_benchmark_test/modelcard.nmos
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@ -5,7 +5,7 @@
** other purposes except for benchmarking the implementation of BSIM-MG ** other purposes except for benchmarking the implementation of BSIM-MG
** against BSIM Team's standard results ** against BSIM Team's standard results
.model nmos1 bsimcmg .model nmos1 NMOS level=17
+ BULKMOD = 1 + BULKMOD = 1
+ CGEOMOD = 0 + CGEOMOD = 0
+ TYPE = 1 + TYPE = 1

2
bsimcmg_benchmark_test/modelcard.nmos.1
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@ -5,7 +5,7 @@
** other purposes except for benchmarking the implementation of BSIM-MG ** other purposes except for benchmarking the implementation of BSIM-MG
** against BSIM Team's standard results ** against BSIM Team's standard results
.model nmos1 bsimcmg .model nmos1 NMOS level=17
+ AGIDL = 50.00f + AGIDL = 50.00f
+ AGISL = 50.00f + AGISL = 50.00f
+ AIGBINV = 11.10m + AIGBINV = 11.10m

2
bsimcmg_benchmark_test/modelcard.pmos
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@ -5,7 +5,7 @@
** other purposes except for benchmarking the implementation of BSIM-MG ** other purposes except for benchmarking the implementation of BSIM-MG
** against BSIM Team's standard results ** against BSIM Team's standard results
.model pmos1 bsimcmg .model pmos1 PMOS level=17
+ BULKMOD = 1 + BULKMOD = 1
+ CGEOMOD = 0 + CGEOMOD = 0
+ TYPE = 0 + TYPE = 0

2
bsimcmg_benchmark_test/modelcard.pmos.1
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@ -5,7 +5,7 @@
** other purposes except for benchmarking the implementation of BSIM-MG ** other purposes except for benchmarking the implementation of BSIM-MG
** against BSIM Team's standard results ** against BSIM Team's standard results
.model pmos1 bsimcmg .model pmos1 PMOS level=17
+ AGIDL =3.000p + AGIDL =3.000p
+ AGISL =3.000p + AGISL =3.000p
+ AIGBINV =11.10m + AIGBINV =11.10m

14
bsimcmg_benchmark_test/ringosc_17stg.sp
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@ -1,10 +1,11 @@
*Sample netlist for BSIM-MG *Sample netlist for BSIM-MG
* (exec-spice "ngspice %s" t)
*17-stage ring oscillator *17-stage ring oscillator
*.options abstol=1e-6 reltol=1e-6 post ingold *.options abstol=1e-6 reltol=1e-6 post ingold
.options abstol=1e-6 reltol=1e-6 post ingold dcon=1 .options abstol=1e-6 reltol=1e-6 post ingold dcon=1
.hdl "bsimcmg.va" *.hdl "bsimcmg.va"
.include "modelcard.nmos" .include "modelcard.nmos"
.include "modelcard.pmos" .include "modelcard.pmos"
@ -13,8 +14,8 @@ vdd supply 0 dc=1.0
* --- Inverter Subcircuit --- * --- Inverter Subcircuit ---
.subckt mg_inv vin vout vdd gnd .subckt mg_inv vin vout vdd gnd
Xp1 vout vin vdd gnd pmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1 mp1 vout vin vdd gnd 0 pmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1
Xn1 vout vin gnd gnd nmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1 mn1 vout vin gnd gnd 0 nmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1
.ends .ends
* --- 17 Stage Ring oscillator --- * --- 17 Stage Ring oscillator ---
@ -37,7 +38,7 @@ Xinv16 16 17 supply 0 mg_inv
Xinv17 17 1 supply 0 mg_inv Xinv17 17 1 supply 0 mg_inv
* --- Initial Condition --- * --- Initial Condition ---
.ic 1=1 .ic v(1)=1
.tran 1p 1n .tran 1p 1n
@ -48,4 +49,9 @@ Xinv17 17 1 supply 0 mg_inv
.measure tran period param'(t2-t1)/3' .measure tran period param'(t2-t1)/3'
.measure tran delay_per_stage param'period/34' .measure tran delay_per_stage param'period/34'
.control
run
plot v(1)
.endc
.end .end