Updated NEWS file
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NEWS
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NEWS
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Ng-spice-rework-13
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Ng-spice-rework-13
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============
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This is a major release in terms of fixes and enhancements.
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A garbage collector support has been added. If the configuration
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script detects that you have installed GC (Bohem-Weiser conservative
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garbage collector), it will use it. Some memory leaks have been
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fixed too.
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Enhancements to the code comes from Alan's contribute code, a
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description of improvements follows (extracted form Alan's mail):
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Output File Format Changes -
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Rawfile format changed to PSPICE Probe format (Usable with
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Demo version of Microsim's Probe).
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(NOTE: Do not rely on this, we may revert to the old format
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in the next release).
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Text mode .OP results even though "rawfile" written.
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Internal device nodes are not saved to "rawfile" (reduces
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file size). Optionally, these internal nodes can be replaced
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by device currents and saved.
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DC Convergence Enhancements -
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"Source-Stepping" algorithm modified with a "Dynamic" step size.
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After each successful step, the node voltages are saved, the
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source-factor is increased by the step-factor, and the step-factor
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is increased (for the next step). If the step fails, i.e. the
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circuit does not converge, the source-factor is set to the value
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from the previous successful step, the previously stored node
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voltages are restored, the step-factor is reduced, the source
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factor is increased by this smaller step-factor, and convergance
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is attempted again.
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Same thing done for "Gmin-stepping" algorithm.
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"Gshunt" option added. This sets the "diagGmin" variable used in
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the gmin-stepping algorithm to a non-zero value for the final
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solution. (Normally this is set to zero for the final solution).
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This helps for circuits with floating nodes (and for some others
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too).
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The Gmin implementation across the substrate diodes of MOS1, MOS2,
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MOS3, MOS6 and BSIM3 devices, and across BJT base-emitter and
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base-collector diodes, was incorrect. Correcting this dramatically
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improved DC convergance. (I think this also effects BSIM1 and 2
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but I haven't fixed them yet !)
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The gm, gmb and gds calculations in the MOS3 model were all wrong.
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The device equations were fixed, leading to much improved
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convergance.
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The Vcrit value used for diode voltage limiting was calculated
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without taking into account the device area (and in some cases
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without using the temperature corrected saturation current).
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This could cause floating point overflows, especially in device
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models designed to be scaled by a small area, e.g. 2u by 2u diodes
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(area=4e-12). This is now fixed for Diode, BJT, MOS1, MOS2, and
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MOS3 models.
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The diode voltage limiting was modified to add negative voltage
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limiting. Negative diode voltages are now limited to 3*Vdp-10,
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where Vdp is the voltage from the previous iteration. If Vdp is
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positive, then the voltage is limited to -10V. This prevents some
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more floating point overflows. (Actually, I'm still playing with
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the best values for this).
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The Spice3 "fix" for the MOS3 gds discontinuity between the
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linear and saturated regions only works if the VMAX parameter
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is non-zero. A "tweak" has been added for the VMAX=0 case.
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Transient Convergance Enhancements -
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Temperature correction of various diode capacitances was implemented
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slightly incorrectly, leading to capacitance discontinuities in
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simulations at temperatures other than nominal. This affected the
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Diode and MOS3 models.
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A mistake in the implementation of the MOS3 source-bulk capacitance
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model resulted in a charge storage discontinuity. This has been fixed.
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The level 2 MOSFET model seems to calculate Von and Vth values for
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the threshold and subthreshold values respectively, but then uses
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Vbin to calculate the Vdsat voltage used to find the drain current.
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However, a jump statement uses Von to decide that the device is in
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the "cutoff" region, which means that when this jump allows the
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drain current to be calculated, Vdsat can already be well above
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zero. This leads to a discontinuity of drain current with respect
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to gate voltage. The code is now modified to use Vbin for the jump
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decision. It looks like the code should actually use Vth as the
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threshold voltage, but since PSPICE and HSPICE both follow the
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original Berkeley code, this was left alone.
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New Model Parameters -
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A PSPICE/HSPICE-like "M" device parameter (i.e. M devices in
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parallel) was added to the MOS1,2,3 and BSIM3 mosfet models.
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Input Read-in and Checking -
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Numbers beginning with a + sign got the input routine confused.
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Fixed now.
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Attempts to nodeset (or .IC) non-existant nodes are flagged with a
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warning.
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PWL statements on Voltage or Current sources are now checked for
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"non-increasing" time-points at the start of the simulation.
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Previously each time-point was checked as it was reached during
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the simulation, which could be very annoying if you made a mistake
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which caused the simulation to fail after hours of run-time.
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A check which was performed at the end of each sub-circuit expansion
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was moved to the top level. This check makes sure that all sub-circuits
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have been defined, but in its original position, it meant that if a
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sub-circuit included ANY .MODEL statements at all, then ALL the models
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called in that sub-circuit must also be defined within that
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sub-circuit. Now SPICE behaves as expected, i.e. a subcircuit may
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define its own models, but may also use models defined at any level
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above.
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Miscellaneous Fixes/Enhancements -
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MOS devices reported only half of the Meyer capacitances, and did not
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include overlap capacitances, when reporting to the .OP printout, or
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when storing device capacitances to the "rawfile".
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The ideal switch devices had no time-step control to stop their
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controlling voltages/currents overshooting the switching thresholds.
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The time-step control has been modified to use the last two time
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points to estimate if the next one will move the controlling
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voltage/current past a switching threshold. If this looks likely,
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then the time-step is reduced.
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The "rawfile" writing routines have been modified to print the
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"reference value" to the console during the simulation. This lets
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the user see exactly how far and how fast the simulation is
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proceeding.
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.OP printout tidied up a lot to make the printout clearer.
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Analysis order changed to fix a "feature" where, if you ask for
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a .OP and a .TRAN in the same simulation, the node voltages
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printed out correspond to the .OP, but the device data was from
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the last timepoint of the .TRAN
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Etc. -
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There are other minor bug fixes, and changes to reduce compiler
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warnings. There are probably some more significant fixes which
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I've forgotten :-)
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This release c
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Ng-spice-rework-12
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Ng-spice-rework-12
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============
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============
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