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ngspice
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Merge branch 'pre-master-43' into bt_dev

This commit is contained in:
Brian Taylor 2024-01-15 07:14:26 -08:00
parent 7f3cd34e69 a0bddf872d
commit 82cfd464d4
8 changed files with 50 additions and 31 deletions
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1
src/frontend/inpcom.c
View File

@ -8035,7 +8035,6 @@ static int inp_vdmos_model(struct card *deck)
wl_append_word(NULL, &wl, token);
else {
tfree(token);
break;
}
if (*cut_line == ')' || *cut_line == '\0') {
wl_append_word(NULL, &wl, copy(")"));

7
src/maths/KLU/klusmp.c
View File

@ -535,6 +535,10 @@ SMPcLUfac (SMPmatrix *Matrix, double PivTol)
if (ret == 0)
{
if (Matrix->SMPkluMatrix->KLUmatrixCommon == NULL) {
fprintf(stderr, "Error (ReFactor Complex): KLUcommon object is NULL. A problem occurred\n");
return 0 ;
}
if (Matrix->SMPkluMatrix->KLUmatrixCommon->status == KLU_SINGULAR) {
if (ft_ngdebug) {
fprintf(stderr, "Warning (ReFactor Complex): KLU Matrix is SINGULAR\n");
@ -543,9 +547,6 @@ SMPcLUfac (SMPmatrix *Matrix, double PivTol)
}
return E_SINGULAR ;
}
if (Matrix->SMPkluMatrix->KLUmatrixCommon == NULL) {
fprintf (stderr, "Error (ReFactor Complex): KLUcommon object is NULL. A problem occurred\n") ;
}
if (Matrix->SMPkluMatrix->KLUmatrixCommon->status == KLU_EMPTY_MATRIX)
{
fprintf (stderr, "Error (ReFactor Complex): KLU Matrix is empty\n") ;

2
src/spicelib/analysis/cktop.c
View File

@ -409,7 +409,7 @@ new_gmin(CKTcircuit* ckt, long int firstmode,
}
if (iters > (3 * ckt->CKTdcTrcvMaxIter / 4))
factor = MAX(sqrt(factor), 1.00005);
factor = MAX(sqrt(factor), 3);
OldGmin = ckt->CKTgmin;

11
src/spicelib/devices/dio/diosetup.c
View File

@ -197,9 +197,14 @@ DIOsetup(SMPmatrix *matrix, GENmodel *inModel, CKTcircuit *ckt, int *states)
if((!model->DIOresistGiven) || (model->DIOresist==0)) {
if (newcompat.ps || newcompat.lt) {
model->DIOconductance = 1e4; /* improved convergence */
if (ft_ngdebug)
fprintf(stderr, "Diode series resistance in model %s set to 100 microOhm\n", model->gen.GENmodName);
double rsdiode = 0.;
if (cp_getvar("rsdiode", CP_REAL, &rsdiode, 0) && rsdiode > 0) {
model->DIOconductance = 1./rsdiode; /* sometimes improves convergence */
if (ft_ngdebug)
fprintf(stderr, "Diode series resistance in model %s set to 100 microOhm\n", model->gen.GENmodName);
}
else
model->DIOconductance = 0.0;
}
else
model->DIOconductance = 0.0;

23
src/spicelib/devices/tra/traacct.c
View File

@ -107,19 +107,16 @@ TRAaccept(CKTcircuit *ckt, GENmodel *inModel)
here->TRAabstol) ||
(fabs(d3-d4) >= here->TRAreltol*MAX(fabs(d3),fabs(d4))+
here->TRAabstol) ) {
/* derivitive changing - need to schedule after delay */
/*printf("%s: at %g set for %g\n",here->TRAname,
ckt->CKTtime,
*(here->TRAdelays+3*here->TRAsizeDelay-3)+here->TRAtd
);*/
/*printf("%g, %g, %g -> %g, %g \n",v1,v2,v3,d1,d2);*/
/*printf("%g, %g, %g -> %g, %g \n",v4,v5,v6,d3,d4);*/
/* also set for break after PREVIOUS point */
/*printf("setting break\n");*/
error = CKTsetBreak(ckt,
*(here->TRAdelays+3*here->TRAsizeDelay -3) +
here->TRAtd);
if(error) return(error);
double when;
/* Derivative changed - need to schedule after delay */
when = *(here->TRAdelays + 3 * here->TRAsizeDelay - 3) +
here->TRAtd;
if (when > ckt->CKTtime) {
error = CKTsetBreak(ckt, when);
if(error) return(error);
}
}
#endif /*NOTDEF*/
}

33
src/spicelib/devices/vsrc/vsrcacct.c
View File

@ -92,7 +92,7 @@ VSRCaccept(CKTcircuit *ckt, GENmodel *inModel)
}
if (ckt->CKTtime >= here->VSRCbreak_time) {
double wait;
double wait, atime;
if (time >= PER) {
/* Repeating signal: where in period are we? */
@ -101,26 +101,35 @@ VSRCaccept(CKTcircuit *ckt, GENmodel *inModel)
time -= basetime;
}
/* A request for a breakpoint very close
* to the current time will be ignored.
* Adjust so the next corner will be
* selected.
*/
atime = time + ckt->CKTminBreak;
/* Set next breakpoint. */
if (time < 0.0) {
if (atime < 0.0) {
/* Await first pulse */
wait = -time;
} else if (time < TR) {
} else if (atime < TR) {
/* Wait for end of rise. */
wait = TR - time;
} else if (time < TR + PW) {
} else if (atime < TR + PW) {
/* Wait for fall. */
wait = TR + PW - time;
} else if (time < TR + PW + TF) {
} else if (atime < TR + PW + TF) {
/* Wait for end of fall. */
wait = TR + PW + TF - time;
} else {
/* Wait for next pulse. */
wait = PER - time;
}
here->VSRCbreak_time = ckt->CKTtime + wait;
@ -160,7 +169,7 @@ VSRCaccept(CKTcircuit *ckt, GENmodel *inModel)
case PWL:
if (ckt->CKTtime >= here->VSRCbreak_time) {
double time, end, period;
double time, atime, end, period;
int i;
time = ckt->CKTtime - here->VSRCrdelay;
@ -183,10 +192,18 @@ VSRCaccept(CKTcircuit *ckt, GENmodel *inModel)
}
}
/* A request for a breakpoint very close
* to the current time will be ignored.
* Adjust so the next corner will be
* selected.
*/
atime = time + ckt->CKTminBreak;
for (i = 0;
i < here->VSRCfunctionOrder;
i += 2) {
if (here->VSRCcoeffs[i] > time) {
if (here->VSRCcoeffs[i] > atime) {
here->VSRCbreak_time =
ckt->CKTtime +
here->VSRCcoeffs[i] - time;
@ -257,7 +274,7 @@ VSRCaccept(CKTcircuit *ckt, GENmodel *inModel)
if (ckt->CKTtime >=
state->RTScapTime - ckt->CKTminBreak &&
ckt->CKTtime <=
state->RTScapTime + ckt->CKTminBreak) {
state->RTScapTime + ckt->CKTminBreak) {
error = CKTsetBreak(ckt, state->RTSemTime);
if(error)
return(error);

2
visualc/make-install-vngspice.bat
View File

@ -34,7 +34,7 @@ goto end
:b64
set dst=c:\Spice64_KLU
set dst=c:\Spice64
set cmsrc=.\codemodels\x64\Release
mkdir %dst%\bin

2
visualc/make-install-vngspiced.bat
View File

@ -34,7 +34,7 @@ goto end
:b64
set dst=c:\Spice64d_KLU
set dst=c:\Spice64d
set cmsrc=.\codemodels\x64\Debug
mkdir %dst%\bin