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2003-08-31 Stefan Jones <stefan.jones@multigig.com> 

* tests/TransImpedanceAmp/output.net:
	processed with dos2unix

	* configure.in src/spinit.in src/spinit
	src/xspice/cmpp/Makefile src/xspice/cmpp/Makefile.in:
	Make configure automatically set paths for lex yacc and install dir

2003-08-30 Stefan Jones <stefan.jones@multigig.com>

	* src/Makefile.am Makefile.am README.Tcl
	src/xspice/README src/xspice/icm/README
	src/xspice/icm/spice2poly/icm_spice2poly/README:
	Updated to reflect codemodel support is now complete

	* src/xspice/{Makefile.am,xspice.c}
	src/xspice/cm/{cmexport.c,Makefile.am}:
	Moved the xspice library hooks into the cm directory

	* src/Makefile.am src/ngspice.idx:
	Remove ngspice.idx and make it auto-generated and installed
This commit is contained in:
stefanjones 2003-08-31 12:27:27 +00:00
parent b09844e956
commit 7f3cb33f8c
18 changed files with 517 additions and 575 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
ChangeLog
View File

@ -1,5 +1,26 @@
2003-08-31 Stefan Jones <stefan.jones@multigig.com>
* tests/TransImpedanceAmp/output.net:
processed with dos2unix
* configure.in src/spinit.in src/spinit
src/xspice/cmpp/Makefile src/xspice/cmpp/Makefile.in:
Make configure automatically set paths for lex yacc and install dir
2003-08-30 Stefan Jones <stefan.jones@multigig.com>
* src/Makefile.am Makefile.am README.Tcl
src/xspice/README src/xspice/icm/README
src/xspice/icm/spice2poly/icm_spice2poly/README:
Updated to reflect codemodel support is now complete
* src/xspice/{Makefile.am,xspice.c}
src/xspice/cm/{cmexport.c,Makefile.am}:
Moved the xspice library hooks into the cm directory
* src/Makefile.am src/ngspice.idx:
Remove ngspice.idx and make it auto-generated and installed
* configure.in:
Change version to 0.2.14

2
Makefile.am
View File

@ -19,5 +19,3 @@ tcl:
install-tcl:
cd src && $(MAKE) install-tcl
codemodels:
cd src/xspice/icm && make

4
README.Tcl
View File

@ -52,10 +52,12 @@ and based upon the NG-Spice source code base with many improvements
** More information:
tclspice/src/tcl/README : more in depth information on how to create your
src/tcl/README : more in depth information on how to create your
own Tcl scripts.
Example also supplied in the same directory (vector_test.tcl).
src/xspice/README : More details on the xspice additions / useage
http://tclspice.sourceforge.net/ : Homepage of Tclspice
Stefan Jones <stefan.jones@multigig.com>

9
configure.in
View File

@ -402,9 +402,10 @@ dnl Add new code models to the build by pointing to them here.
if test "$enable_xspice" = "yes"; then
AC_MSG_RESULT(X-Spice features included)
AC_DEFINE(XSPICE)
AC_PROG_YACC
AM_PROG_LEX
XSPICEDIR="xspice"
XSPICELIB1="$XSPICEDIR/xspice.o \
$XSPICEDIR/mif/libmifxsp.a \
XSPICELIB1="$XSPICEDIR/mif/libmifxsp.a \
$XSPICEDIR/cm/libcmxsp.a"
XSPICELIB2="$XSPICEDIR/evt/libevtxsp.a \
$XSPICEDIR/enh/libenhxsp.a \
@ -415,7 +416,7 @@ if test "$enable_xspice" = "yes"; then
else
XSPCIEDIR=""
XSPICELIB1=""
XSPICELIB2=""
XSPICELIB2=""
fi
AC_SUBST(XSPICEDIR)
AC_SUBST(XSPICELIB1)
@ -443,6 +444,7 @@ doc/Makefile \
man/Makefile \
man/man1/Makefile \
src/Makefile \
src/spinit \
src/spicelib/Makefile \
src/spicelib/analysis/Makefile \
src/spicelib/devices/Makefile \
@ -503,6 +505,7 @@ src/maths/sparse/Makefile \
src/misc/Makefile \
src/xspice/Makefile \
src/xspice/cm/Makefile \
src/xspice/cmpp/Makefile \
src/xspice/icm/makedefs \
src/xspice/mif/Makefile \
src/xspice/evt/Makefile \

16
src/Makefile.am
View File

@ -8,7 +8,7 @@ EXTRA_DIST = ngspice.txt spinit setplot spectrum
helpdatadir = $(pkgdatadir)/helpdir
helpdata_DATA = ngspice.txt
helpdata_DATA = ngspice.txt ngspice.idx
initdatadir = $(pkgdatadir)/scripts
@ -59,15 +59,6 @@ DYNAMIC_DEVICELIBS = \
spicelib/devices/vcvs/libvcvs.a \
spicelib/devices/vsrc/libvsrc.a
## ----- Note that I moved this stuff to here because it was causing automake
## to choke when it was in the DYNAMIC_DEVICELIBS list above -----
## This lib deleted from DYNAMIC_DEVICELIBS by sdb 'cause there's no source for it.
## spicelib/devices/bjt2/libbjt2.a \
## poly added to dynamic libs by SDB on 6.1.2003
## xspice/icm/poly/libpoly.a
## Build ngspice first:
ngspice_SOURCES = \
@ -159,12 +150,9 @@ ngmultidec_LDADD = \
makeidx_SOURCES = makeidx.c
makeidx_LDADD = \
misc/libmisc.a
## create index for online help:
all:
ngspice.idx: makeidx
./makeidx $(srcdir)/ngspice.txt

10
src/makeidx.c
View File

@ -4,13 +4,13 @@ Copyright 1990 Regents of the University of California. All rights reserved.
/* from FILENAME.txt, make FILENAME.idx */
#include "ngspice.h"
#include <stdio.h>
#include "cpdefs.h"
#include "hlpdefs.h"
#include "suffix.h"
#include <string.h>
#include <stdlib.h>
#include <defines.h>
#include <cpextern.h>
#include <hlpdefs.h>
int
main(argc, argv)

BIN
src/ngspice.idx
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Binary file not shown.

13
src/spinit
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@ -1,13 +0,0 @@
* Standard spice and nutmeg init file
alias exit quit
alias acct rusage all
set x11lineararcs
* For SPICE2 POLYs, edit the below line to point to the location
* of your codemode.
* codemodel /usr/lib/spice/spice2poly.cm
* The other codemodels
* codemodel /usr/lib/spice/analog.cm
* codemodel /usr/lib/spice/digital.cm
* codemodel /usr/lib/spice/xtradev.cm
* codemodel /usr/lib/spice/xtraevt.cm

13
src/spinit.in Normal file
View File

@ -0,0 +1,13 @@
* Standard spice and nutmeg init file
alias exit quit
alias acct rusage all
set x11lineararcs
* For SPICE2 POLYs, edit the below line to point to the location
* of your codemode.
* codemodel @prefix@/lib/spice/spice2poly.cm
* The other codemodels
* codemodel @prefix@/lib/spice/analog.cm
* codemodel @prefix@/lib/spice/digital.cm
* codemodel @prefix@/lib/spice/xtradev.cm
* codemodel @prefix@/lib/spice/xtraevt.cm

8
src/xspice/Makefile.am
View File

@ -1,7 +1,4 @@
# Process this file with automake
CFLAGS = -g -O2 -Wall
CC = gcc
COMPILE = $(CC) $(DEFS) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
EXTRA_DIST = README
@ -11,10 +8,5 @@ EXTRA_DIST = README
SUBDIRS = mif cm enh evt ipc idn cmpp icm
INCLUDES = -I$(top_srcdir)/src/include -I$(top_srcdir)
MAINTAINERCLEANFILES = Makefile.in
all: xspice.o
xspice.o:
$(COMPILE) -c xspice.c

78
src/xspice/README
View File

@ -1,41 +1,79 @@
Spice Opus / XSpice code model support.
--------------------------------------
Use configure flag --enable-xspice to compile the support in,
Use configure the flag --enable-xspice to compile xspice support in,
when you run the ./configure script.
This creates a new command, "codemodel", which you can
use to load a codemodel.
Some codemodels are included in the xspice/lib directory
with some examples in xspice/examples, compiled for linux glibc.
The command codemodel attempts to load all the codemodels specified in the
arguments, eg
"ngspice 1 ->codemodel /usr/lib/spice/analog.cm /usr/lib/spice/spice2poly.cm"
Make sure the the library dir, xspice/lib, is in your LD_LIBRARY_PATH
enviromental variable, otherwise the libs will not be found!
( note: the codemodel path must begin with ./ or / to work )
To create codemodels go to http://www.fe.uni-lj.si/spice/welcome.html
and download their trial version of spice opus for the codemodel toolkit!
The codemodels are automatically compiled and then installed in
${prefix}/lib/spice/ when spice is installed.
TODO:
Intergrate the ipc stuff from XSpice.
Create ng-spice capacity to create codemodels (a perl script)
Ngspice crashes when you try to plot a digital node
To create your own codemodels:
* Unpack the tclspice source and compile as normal.
* cd src/xspice/icm
* make the directory structure for the new library:
Create the nested library_name and module_name directories and copy the
source code to the module_name directories
src/xspice/icm/ <library_name> /
modpath.lst udnpath.lst
<module_name> /
files:
cfunc.mod ifspec.ifs ( for a device )
or
udnfunc.c ( or a user defined node )
* For each library create the files modpath.lst and udnpath.lst, which
contain a list of the user devices and nodes respectivily, in the location
shown above.
* Edit src/xspice/icm/makedefs.in and alter the CMDIRS line to include
your library directory.
* Run make in the src/xspice/icm directory. ( the makefile does the rest )
The codemodel can be then found in
src/xspice/icm/<library_name>/<library_name>.cm
Stefan Jones
19/2/2002
20020219
Edited 20030831
-----------------------------------------
SPICE2 POLY codemodel support.
SPICE2 POLY attributes are now available for controlled sources. To
use POLY attributes, configure tclspice/ngspice with the
--enable-xspice flag set as described above. After compilation of
ngspice, cd into $(top_srcdir)/src/xspice/icm and read the README file
there for instructions about how to get POLY support. (Hint: you have
to download some stuff from http://www.fe.uni-lj.si/ and edit the
Makefiles before you can do "make && make install" of the codemodel
stuff.)
SPICE2 POLY attributes are now available for controlled sources.
To use POLY attributes, configure and install ( make install-tcl )
tclspice/ngspice with the --enable-xspice flag set as described above.
After compilation of ngspice edit
${prefix}/share/tclspice/scripts/spinit or
${prefix}/share/ngspice/scripts/spinit
( depending if you included tcl support or not )
and uncomment the
"* codemodel /usr/lib/spice/spice2poly.cm"
line and edit as required. ( the path to spice2poly.cm may be wrong )
( alternativily create a ~/.spiceinit file with the above codemodel line )
Then read in your SPICE netlist. SPICE 2 POLY attributes in
controlled sources will be translated into .models invoking the
spice2poly codemodel. You should be able to run ngspice and simulate
in the usual way!
Please direct questions/comments/complaints to mailto:sdb@cloud9.net.
6.22.2003 -- SDB.
Edited on 20030831 by Stefan Jones

3
src/xspice/cm/Makefile.am
View File

@ -8,7 +8,8 @@ libcmxsp_a_SOURCES = \
cm.c \
cmevt.c \
cmmeters.c \
cmutil.c
cmutil.c \
cmexport.c

2
src/xspice/xspice.c → src/xspice/cm/cmexport.c
View File

@ -5,7 +5,7 @@
/*how annoying!, needed for structure below*/
void *tcalloc(size_t a, size_t b){
static void *tcalloc(size_t a, size_t b){
return tmalloc(a*b);
}

12
src/xspice/cmpp/Makefile → src/xspice/cmpp/Makefile.in
View File

@ -1,18 +1,18 @@
cmpp_OBJS=main.o pp_ifs.o pp_lst.o pp_mod.o read_ifs.o util.o writ_ifs.o \
cmpp_OBJS = main.o pp_ifs.o pp_lst.o pp_mod.o \
read_ifs.o util.o writ_ifs.o \
ifs_yacc.o ifs_lex.o mod_yacc.o mod_lex.o
cmpp_GEN=ifs_yacc.c ifs_tok.h \
cmpp_GEN = ifs_yacc.c ifs_tok.h \
ifs_lex.c ifs_lex.h \
mod_lex.c mod_lex.h \
mod_yacc.c mod_tok.h
YACC=bison -d --yacc
#YACC=yacc -d
YACC = @YACC@ -d
CC=gcc -O2 -g
CC = @CC@ @CFLAGS@
LEX=flex -t
LEX = @LEX@ -t
all: cmpp

36
src/xspice/icm/Makefile
View File

@ -21,10 +21,10 @@ COMPILE = $(CC) $(INCLUDES) $(CFLAGS)
INSTALL_DATA = ${INSTALL} -m 644
all:
@amf=$$2; for x in $(CMDIRS) ; do \
@for x in $(CMDIRS) ; do \
( cd $$x && $(UPMAKE) $$x-mods ) \
|| case "$$amf" in *=*) exit 1;; *k*) fail=yes;; *) exit 1;; esac; \
done && test -z "$$fail"
|| exit 1; \
done
install: all
$(mkinstalldirs) $(DESTDIR)$(libdir)/spice
@ -35,10 +35,10 @@ install: all
done
clean:
@amf=$$2; for x in $(CMDIRS) ; do \
@for x in $(CMDIRS) ; do \
( cd $$x && $(UPMAKE) $$x-mods-clean ) \
|| case "$$amf" in *=*) exit 1;; *k*) fail=yes;; *) exit 1;; esac; \
done && test -z "$$fail"
|| exit 1; \
done
-rm -rf .deps
ifspec.c: ifspec.ifs
@ -68,26 +68,26 @@ dlmain.o: cmextrn.h cminfo.h udnextrn.h udninfo.h
$(COMPILE) $(LDFLAGS) -o $@ `awk '{ print $$1 }' objects.inc` dlmain.o
%-mods: modpath.lst udnpath.lst
@amf=$$2; for x in `cat modpath.lst` ; do \
@for x in `cat modpath.lst` ; do \
( cd $$x && $(UPMAKE) objs ) \
|| case "$$amf" in *=*) exit 1;; *k*) fail=yes;; *) exit 1;; esac; \
done && test -z "$$fail"
@amf=$$2; for x in `cat udnpath.lst` ; do \
|| exit 1; \
done
@for x in `cat udnpath.lst` ; do \
( cd $$x && $(UPMAKE) uobjs ) \
|| case "$$amf" in *=*) exit 1;; *k*) fail=yes;; *) exit 1;; esac; \
done && test -z "$$fail"
|| exit 1; \
done
@target=`echo $@ | sed s/-mods//`; $(MAKE) $$target.cm
%-mods-clean:
@target=`echo $@ | sed s/-mods-clean//` && rm -f $$target.cm
@amf=$$2; for x in `cat modpath.lst` ; do \
@for x in `cat modpath.lst` ; do \
( cd $$x && $(UPMAKE) objs-clean ) \
|| case "$$amf" in *=*) exit 1;; *k*) fail=yes;; *) exit 1;; esac; \
done && test -z "$$fail"
@amf=$$2; for x in `cat udnpath.lst` ; do \
|| exit 1; \
done
@for x in `cat udnpath.lst` ; do \
( cd $$x && $(UPMAKE) uobjs-clean ) \
|| case "$$amf" in *=*) exit 1;; *k*) fail=yes;; *) exit 1;; esac; \
done && test -z "$$fail"
|| exit 1; \
done
-rm -f cmextrn.h cminfo.h objects.inc udnextrn.h udninfo.h \
dlmain.c dlmain.o
-rm -rf .deps

52
src/xspice/icm/README
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@ -1,52 +0,0 @@
This directory holds a codemodel which enables ngspice to handle SPICE
2 POLY attributes on controlled sources. In short, when a SPICE 2
netlist is read in, any controlled sources with POLY attributes are
translated into codemodel devices with an associated .model which
invokes spice2poly to evaluate the polynomial.
To use this model, you need to do the following:
1. Compile the rest of ngspice/tclspice in the usual way from the
base directory. Make sure you do configure --enable-xspice when
configuring.
2. Download and install SPICE Opus (available from
http://www.fe.uni-lj.si/). From this you need the program cmpp, as
well as some of the include files.
3. Edit the Makefile in this directory and make the variable CMPPDIR
point to the base location of your Opus installation. (Hint: I
place it in /usr/local/opus.)
4. Edit the Makefile in the directory below (icm_spice2poly/) and
make the variable CMPDIR point to the base location of your Opus
installation.
5. Do "make" in this directory. The makefiles are set up
to do all the necessary stuff to turn the spice2poly sources into a
shared object named spice2poly.cm which you can load into ngspice.
(Alternatively, you can do "make codemodels" from $(top_srcdir); I
have included codemodels as a target which cd's into this directory
and does "make".)
6. Read the codemodel into ngspice in the following way:
ngspice 1 -> codemodel /usr/local/src/tclspice-0.2.10/src/xspice/icm/spice2poly.cm
(Of course, you should point to the location where *you* built
spice2poly.cm!) You might want to put this invocation into your
spinit file (which usually lives in $(top_srcdir)/src/).
7. Then read in your SPICE netlist. SPICE 2 POLY attributes in
controlled sources will be translated into .models invoking the
spice2poly codemodel. You should be able to run ngspice and simulate
in the usual way!
----------------------------------------------------------------------
Please send any comments/questions/bug reports to:
Stuart Brorson
sdb@cloud9.net
-- SDB 6.19.2003

49
src/xspice/icm/spice2poly/icm_spice2poly/README
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@ -1,49 +0,0 @@
This directory holds a codemodel which enables ngspice to handle SPICE
2 POLY attributes on controlled sources. In short, when a SPICE 2
netlist is read in, any controlled sources with POLY attributes are
translated into codemodel devices with an associated .model which
invokes spice2poly to evaluate the polynomial.
To use this model, you need to do the following:
1. Compile the rest of ngspice/tclspice in the usual way from the
base directory.
2. Download and install SPICE Opus (available from
http://www.fe.uni-lj.si/ ). From this you need the program cmpp, as
well as some of the include files.
3. Edit the Makefile in this directory and make the variable CMPPDIR
point to the base location of your Opus installation.
4. Edit the Makefile in the directory above (..) and make the
variable CMPDIR point to the base location of your Opus installation.
5. Do "make" in the directory above (..). The makefiles are set up
to do all the necessary stuff to turn the spice2poly sources into a
shared object named spice2poly.cm which you can load into ngspice.
(Alternatively, you can do "make codemodels" from $(top_srcdir); I
have included codemodels as a target which cd's into the directory
below and does "make".)
6. Read the codemodel into ngspice in the following way:
ngspice 1 -> codemodel /usr/local/src/tclspice-0.2.10/src/xspice/icm/spice2poly.cm
(Of course, you should point to the location where *you* built
spice2poly.cm!) You might want to put this invocation into your
spinit file (which usually lives in $(top_srcdir)/src/).
7. Then read in your SPICE netlist. SPICE 2 POLY attributes in
controlled sources will be translated into .models invoking the
spice2poly codemodel. You should be able to run ngspice and simulate
in the usual way!
----------------------------------------------------------------------
Please send any comments/questions/bug reports to:
Stuart Brorson
sdb@cloud9.net
-- SDB 6.19.2003

764
tests/TransImpedanceAmp/output.net
View File

@ -22,248 +22,248 @@ R201 -5V 9 22
Rref1in VU100in- VU780out 9130
Rref1fb VU1bias+ VU100in- 33
XU101 +5V 7 0 6 VU780out 8 AD780A
* AD780A SPICE Macromodel 5/93, Rev. A
* AAG / PMI
*
* This version of the AD780 voltage reference model simulates the worst case
* parameters of the 'A' grade. The worst case parameters used
* correspond to those in the data sheet.
*
* Copyright 1993 by Analog Devices, Inc.
*
* Refer to "README.DOC" file for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* NODE NUMBERS
* VIN
* | TEMP
* | | GND
* | | | TRIM
* | | | | VOUT
* | | | | | RANGE
* | | | | | |
.SUBCKT AD780A 2 3 4 5 6 8
*
* BANDGAP REFERENCE
*
I1 4 40 DC 1.21174E-3
R1 40 4 1E3 TC=7E-6
EN 10 40 42 0 1
G1 4 10 2 4 4.85668E-9
F1 4 10 POLY(2) VS1 VS2 (0,2.42834E-5,3.8E-5)
Q1 2 10 11 QT
I2 11 4 DC 12.84E-6
R2 11 3 1E3
I3 3 4 DC 0
*
* NOISE VOLTAGE GENERATOR
*
VN1 41 0 DC 2
DN1 41 42 DEN
DN2 42 43 DEN
VN2 0 43 DC 2
*
* INTERNAL OP AMP
*
G2 4 12 10 20 1.93522E-4
R3 12 4 2.5837E9
C1 12 4 6.8444E-11
D1 12 13 DX
V1 2 13 DC 1.2
*
* SECONDARY POLE @ 508 kHz
*
G3 4 14 12 4 1E-6
R4 14 4 1E6
C2 14 4 3.1831E-13
*
* OUTPUT STAGE
*
ISY 2 4 6.8282E-4
FSY 2 4 V1 -1
RSY 2 4 500E3
*
G4 4 15 14 4 25E-6
R5 15 4 40E3
Q2 4 15 16 QP
I4 2 16 DC 100E-6
Q3 4 16 18 QP
R6 18 23 15
R7 16 21 150E3
R8 2 17 34.6
Q4 17 16 19 QN
R9 21 20 6.46E3
R10 20 4 6.1E3
R11 20 5 53E3
R12 20 8 15.6E3
I5 5 4 DC 0
I6 8 4 DC 0
VS1 21 19 DC 0
VS2 23 21 DC 0
L1 21 6 1E-7
*
* OUTPUT CURRENT LIMIT
*
FSC 15 4 VSC 1
VSC 2 22 DC 0
QSC 22 2 17 QN
*
.MODEL QT NPN(IS=1.68E-16 BF=1E4)
.MODEL QN NPN(IS=1E-15 BF=1E3)
.MODEL QP PNP(IS=1E-15 BF=1E3)
.MODEL DX D(IS=1E-15)
.MODEL DEN D(IS=1E-12 RS=2.425E+05 AF=1 KF=6.969E-16)
.ENDS AD780A
* AD780A SPICE Macromodel 5/93, Rev. A
* AAG / PMI
*
* This version of the AD780 voltage reference model simulates the worst case
* parameters of the 'A' grade. The worst case parameters used
* correspond to those in the data sheet.
*
* Copyright 1993 by Analog Devices, Inc.
*
* Refer to "README.DOC" file for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* NODE NUMBERS
* VIN
* | TEMP
* | | GND
* | | | TRIM
* | | | | VOUT
* | | | | | RANGE
* | | | | | |
.SUBCKT AD780A 2 3 4 5 6 8
*
* BANDGAP REFERENCE
*
I1 4 40 DC 1.21174E-3
R1 40 4 1E3 TC=7E-6
EN 10 40 42 0 1
G1 4 10 2 4 4.85668E-9
F1 4 10 POLY(2) VS1 VS2 (0,2.42834E-5,3.8E-5)
Q1 2 10 11 QT
I2 11 4 DC 12.84E-6
R2 11 3 1E3
I3 3 4 DC 0
*
* NOISE VOLTAGE GENERATOR
*
VN1 41 0 DC 2
DN1 41 42 DEN
DN2 42 43 DEN
VN2 0 43 DC 2
*
* INTERNAL OP AMP
*
G2 4 12 10 20 1.93522E-4
R3 12 4 2.5837E9
C1 12 4 6.8444E-11
D1 12 13 DX
V1 2 13 DC 1.2
*
* SECONDARY POLE @ 508 kHz
*
G3 4 14 12 4 1E-6
R4 14 4 1E6
C2 14 4 3.1831E-13
*
* OUTPUT STAGE
*
ISY 2 4 6.8282E-4
FSY 2 4 V1 -1
RSY 2 4 500E3
*
G4 4 15 14 4 25E-6
R5 15 4 40E3
Q2 4 15 16 QP
I4 2 16 DC 100E-6
Q3 4 16 18 QP
R6 18 23 15
R7 16 21 150E3
R8 2 17 34.6
Q4 17 16 19 QN
R9 21 20 6.46E3
R10 20 4 6.1E3
R11 20 5 53E3
R12 20 8 15.6E3
I5 5 4 DC 0
I6 8 4 DC 0
VS1 21 19 DC 0
VS2 23 21 DC 0
L1 21 6 1E-7
*
* OUTPUT CURRENT LIMIT
*
FSC 15 4 VSC 1
VSC 2 22 DC 0
QSC 22 2 17 QN
*
.MODEL QT NPN(IS=1.68E-16 BF=1E4)
.MODEL QN NPN(IS=1E-15 BF=1E3)
.MODEL QP PNP(IS=1E-15 BF=1E3)
.MODEL DX D(IS=1E-15)
.MODEL DEN D(IS=1E-12 RS=2.425E+05 AF=1 KF=6.969E-16)
.ENDS AD780A
C101 0 U100V- 1uF
C102 U100V+ 0 1uF
XU100 0 VU100in- U100V+ U100V- VU1bias+ OP177A
* OP177A SPICE Macro-model 12/90, Rev. B
* JCB / PMI
*
* Revision History:
* REV. B
* Re-ordered subcircuit call out nodes to put the
* output node last.
* Changed Ios from 1E-9 to 0.5E-9
* Added F1 and F2 to fix short circuit current limit.
*
*
* This version of the OP-177 model simulates the worst case
* parameters of the 'A' grade. The worst case parameters
* used correspond to those in the data book.
*
*
* Copyright 1990 by Analog Devices, Inc.
*
* Refer to "README.DOC" file for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* Node assignments
* non-inverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
* | | | | |
.SUBCKT OP177A 1 2 99 50 39
*
* INPUT STAGE & POLE AT 6 MHZ
*
R1 2 3 5E11
R2 1 3 5E11
R3 5 97 0.0606
R4 6 97 0.0606
CIN 1 2 4E-12
C2 5 6 218.9E-9
I1 4 51 1
IOS 1 2 0.5E-9
EOS 9 10 POLY(1) 30 33 10E-6 1
Q1 5 2 7 QX
Q2 6 9 8 QX
R5 7 4 0.009
R6 8 4 0.009
D1 2 1 DX
D2 1 2 DX
EN 10 1 12 0 1
GN1 0 2 15 0 1
GN2 0 1 18 0 1
*
EREF 98 0 33 0 1
EPLUS 97 0 99 0 1
ENEG 51 0 50 0 1
*
* VOLTAGE NOISE SOURCE WITH FLICKER NOISE
*
DN1 11 12 DEN
DN2 12 13 DEN
VN1 11 0 DC 2
VN2 0 13 DC 2
*
* CURRENT NOISE SOURCE WITH FLICKER NOISE
*
DN3 14 15 DIN
DN4 15 16 DIN
VN3 14 0 DC 2
VN4 0 16 DC 2
*
* SECOND CURRENT NOISE SOURCE
*
DN5 17 18 DIN
DN6 18 19 DIN
VN5 17 0 DC 2
VN6 0 19 DC 2
*
* FIRST GAIN STAGE
*
R7 20 98 1
G1 98 20 5 6 119.8
D3 20 21 DX
D4 22 20 DX
E1 97 21 POLY(1) 97 33 -2.4 1
E2 22 51 POLY(1) 33 51 -2.4 1
*
* GAIN STAGE & DOMINANT POLE AT 0.127 HZ
*
R8 23 98 1.253E9
C3 23 98 1E-9
G2 98 23 20 33 33.3E-6
V1 97 24 1.8
V2 25 51 1.8
D5 23 24 DX
D6 25 23 DX
*
* NEGATIVE ZERO AT -4MHZ
*
R9 26 27 1
C4 26 27 -39.75E-9
R10 27 98 1E-6
E3 26 98 23 33 1E6
*
* COMMON-MODE GAIN NETWORK WITH ZERO AT 63 HZ
*
R13 30 31 1
L2 31 98 2.52E-3
G4 98 30 3 33 0.316E-6
D7 30 97 DX
D8 51 30 DX
*
* POLE AT 2 MHZ
*
R14 32 98 1
C5 32 98 79.5E-9
G5 98 32 27 33 1
*
* OUTPUT STAGE
*
R15 33 97 1
R16 33 51 1
GSY 99 50 POLY(1) 99 50 0.725E-3 0.0425E-3
F1 34 0 V3 1
F2 0 34 V4 1
R17 34 99 400
R18 34 50 400
L3 34 39 2E-7
G6 37 50 32 34 2.5E-3
G7 38 50 34 32 2.5E-3
G8 34 99 99 32 2.5E-3
G9 50 34 32 50 2.5E-3
V3 35 34 6.8
V4 34 36 4.4
D9 32 35 DX
D10 36 32 DX
D11 99 37 DX
D12 99 38 DX
D13 50 37 DY
D14 50 38 DY
*
* MODELS USED
*
.MODEL QX NPN(BF=333.3E6)
.MODEL DX D(IS=1E-15)
.MODEL DY D(IS=1E-15 BV=50)
.MODEL DEN D(IS=1E-12, RS=14.61K, KF=2E-17, AF=1)
.MODEL DIN D(IS=1E-12, RS=7.55E-6, KF=3E-15, AF=1)
.ENDS
* OP177A SPICE Macro-model 12/90, Rev. B
* JCB / PMI
*
* Revision History:
* REV. B
* Re-ordered subcircuit call out nodes to put the
* output node last.
* Changed Ios from 1E-9 to 0.5E-9
* Added F1 and F2 to fix short circuit current limit.
*
*
* This version of the OP-177 model simulates the worst case
* parameters of the 'A' grade. The worst case parameters
* used correspond to those in the data book.
*
*
* Copyright 1990 by Analog Devices, Inc.
*
* Refer to "README.DOC" file for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* Node assignments
* non-inverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
* | | | | |
.SUBCKT OP177A 1 2 99 50 39
*
* INPUT STAGE & POLE AT 6 MHZ
*
R1 2 3 5E11
R2 1 3 5E11
R3 5 97 0.0606
R4 6 97 0.0606
CIN 1 2 4E-12
C2 5 6 218.9E-9
I1 4 51 1
IOS 1 2 0.5E-9
EOS 9 10 POLY(1) 30 33 10E-6 1
Q1 5 2 7 QX
Q2 6 9 8 QX
R5 7 4 0.009
R6 8 4 0.009
D1 2 1 DX
D2 1 2 DX
EN 10 1 12 0 1
GN1 0 2 15 0 1
GN2 0 1 18 0 1
*
EREF 98 0 33 0 1
EPLUS 97 0 99 0 1
ENEG 51 0 50 0 1
*
* VOLTAGE NOISE SOURCE WITH FLICKER NOISE
*
DN1 11 12 DEN
DN2 12 13 DEN
VN1 11 0 DC 2
VN2 0 13 DC 2
*
* CURRENT NOISE SOURCE WITH FLICKER NOISE
*
DN3 14 15 DIN
DN4 15 16 DIN
VN3 14 0 DC 2
VN4 0 16 DC 2
*
* SECOND CURRENT NOISE SOURCE
*
DN5 17 18 DIN
DN6 18 19 DIN
VN5 17 0 DC 2
VN6 0 19 DC 2
*
* FIRST GAIN STAGE
*
R7 20 98 1
G1 98 20 5 6 119.8
D3 20 21 DX
D4 22 20 DX
E1 97 21 POLY(1) 97 33 -2.4 1
E2 22 51 POLY(1) 33 51 -2.4 1
*
* GAIN STAGE & DOMINANT POLE AT 0.127 HZ
*
R8 23 98 1.253E9
C3 23 98 1E-9
G2 98 23 20 33 33.3E-6
V1 97 24 1.8
V2 25 51 1.8
D5 23 24 DX
D6 25 23 DX
*
* NEGATIVE ZERO AT -4MHZ
*
R9 26 27 1
C4 26 27 -39.75E-9
R10 27 98 1E-6
E3 26 98 23 33 1E6
*
* COMMON-MODE GAIN NETWORK WITH ZERO AT 63 HZ
*
R13 30 31 1
L2 31 98 2.52E-3
G4 98 30 3 33 0.316E-6
D7 30 97 DX
D8 51 30 DX
*
* POLE AT 2 MHZ
*
R14 32 98 1
C5 32 98 79.5E-9
G5 98 32 27 33 1
*
* OUTPUT STAGE
*
R15 33 97 1
R16 33 51 1
GSY 99 50 POLY(1) 99 50 0.725E-3 0.0425E-3
F1 34 0 V3 1
F2 0 34 V4 1
R17 34 99 400
R18 34 50 400
L3 34 39 2E-7
G6 37 50 32 34 2.5E-3
G7 38 50 34 32 2.5E-3
G8 34 99 99 32 2.5E-3
G9 50 34 32 50 2.5E-3
V3 35 34 6.8
V4 34 36 4.4
D9 32 35 DX
D10 36 32 DX
D11 99 37 DX
D12 99 38 DX
D13 50 37 DY
D14 50 38 DY
*
* MODELS USED
*
.MODEL QX NPN(BF=333.3E6)
.MODEL DX D(IS=1E-15)
.MODEL DY D(IS=1E-15 BV=50)
.MODEL DEN D(IS=1E-12, RS=14.61K, KF=2E-17, AF=1)
.MODEL DIN D(IS=1E-12, RS=7.55E-6, KF=3E-15, AF=1)
.ENDS
R102 U100V+ +5V 22
R101 -5V U100V- 22
R98 0 VU2bias+ 1K
@ -290,149 +290,149 @@ R26 2 VU2in- 150
R11 Vout2 VU2in- 180
XU2 VU2bias+ VU2in- V2+ V2- Vout2 AD8009an
XU1 VU1bias+ VU1in- V1+ V1- Vout1 AD8009an
***** AD8009 SPICE model Rev B SMR/ADI 8-21-97
* Copyright 1997 by Analog Devices, Inc.
* Refer to "README.DOC" file for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
* rev B of this model corrects a problem in the output stage that would not
* correctly reflect the output current to the voltage supplies
* This model will give typical performance characteristics
* for the following parameters;
* closed loop gain and phase vs bandwidth
* output current and voltage limiting
* offset voltage (is static, will not vary with vcm)
* ibias (again, is static, will not vary with vcm)
* slew rate and step response performance
* (slew rate is based on 10-90% of step response)
* current on output will be reflected to the supplies
* vnoise, referred to the input
* inoise, referred to the input
* distortion is not characterized
* Node assignments
* non-inverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
* | | | | |
.SUBCKT AD8009an 1 2 99 50 28
* input stage *
q1 50 3 5 qp1
q2 99 5 4 qn1
q3 99 3 6 qn2
q4 50 6 4 qp2
i1 99 5 1.625e-3
i2 6 50 1.625e-3
cin1 1 98 2.6e-12
cin2 2 98 1e-12
v1 4 2 0
* input error sources *
eos 3 1 poly(1) 20 98 2e-3 1
fbn 2 98 poly(1) vnoise3 50e-6 1e-3
fbp 1 98 poly(1) vnoise3 50e-6 1e-3
* slew limiting stage *
fsl 98 16 v1 1
dsl1 98 16 d1
dsl2 16 98 d1
dsl3 16 17 d1
dsl4 17 16 d1
rsl 17 18 0.22
vsl 18 98 0
* gain stage *
f1 98 7 vsl 2
rgain 7 98 2.5e5
cgain 7 98 1.25e-12
dcl1 7 8 d1
dcl2 9 7 d1
vcl1 99 8 1.83
vcl2 9 50 1.83
gcm 98 7 poly(2) 98 0 30 0 0 1e-5 1e-5
* second pole *
epole 14 98 7 98 1
rpole 14 15 1
cpole 15 98 2e-10
* reference stage *
eref 98 0 poly(2) 99 0 50 0 0 0.5 0.5
ecmref 30 0 poly(2) 1 0 2 0 0 0.5 0.5
* vnoise stage *
rnoise1 19 98 4.6e-3
vnoise1 19 98 0
vnoise2 21 98 0.53
dnoise1 21 19 dn
fnoise1 20 98 vnoise1 1
rnoise2 20 98 1
* inoise stage *
rnoise3 22 98 8.18e-6
vnoise3 22 98 0
vnoise4 24 98 0.575
dnoise2 24 22 dn
fnoise2 23 98 vnoise3 1
rnoise4 23 98 1
* buffer stage *
gbuf 98 13 15 98 1e-2
rbuf 98 13 1e2
* output current reflected to supplies *
fcurr 98 40 voc 1
vcur1 26 98 0
vcur2 98 27 0
dcur1 40 26 d1
dcur2 27 40 d1
* output stage *
vo1 99 90 0
vo2 91 50 0
fout1 0 99 poly(2) vo1 vcur1 -9.27e-3 1 -1
fout2 50 0 poly(2) vo2 vcur2 -9.27e-3 1 -1
gout1 90 10 13 99 0.5
gout2 91 10 13 50 0.5
rout1 10 90 2
rout2 10 91 2
voc 10 28 0
rout3 28 98 1e6
dcl3 13 11 d1
dcl4 12 13 d1
vcl3 11 10 -0.445
vcl4 10 12 -0.445
.model qp1 pnp()
.model qp2 pnp()
.model qn1 npn()
.model qn2 npn()
.model d1 d()
.model dn d(af=1 kf=1e-8)
.ends
***** AD8009 SPICE model Rev B SMR/ADI 8-21-97
* Copyright 1997 by Analog Devices, Inc.
* Refer to "README.DOC" file for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
* rev B of this model corrects a problem in the output stage that would not
* correctly reflect the output current to the voltage supplies
* This model will give typical performance characteristics
* for the following parameters;
* closed loop gain and phase vs bandwidth
* output current and voltage limiting
* offset voltage (is static, will not vary with vcm)
* ibias (again, is static, will not vary with vcm)
* slew rate and step response performance
* (slew rate is based on 10-90% of step response)
* current on output will be reflected to the supplies
* vnoise, referred to the input
* inoise, referred to the input
* distortion is not characterized
* Node assignments
* non-inverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
* | | | | |
.SUBCKT AD8009an 1 2 99 50 28
* input stage *
q1 50 3 5 qp1
q2 99 5 4 qn1
q3 99 3 6 qn2
q4 50 6 4 qp2
i1 99 5 1.625e-3
i2 6 50 1.625e-3
cin1 1 98 2.6e-12
cin2 2 98 1e-12
v1 4 2 0
* input error sources *
eos 3 1 poly(1) 20 98 2e-3 1
fbn 2 98 poly(1) vnoise3 50e-6 1e-3
fbp 1 98 poly(1) vnoise3 50e-6 1e-3
* slew limiting stage *
fsl 98 16 v1 1
dsl1 98 16 d1
dsl2 16 98 d1
dsl3 16 17 d1
dsl4 17 16 d1
rsl 17 18 0.22
vsl 18 98 0
* gain stage *
f1 98 7 vsl 2
rgain 7 98 2.5e5
cgain 7 98 1.25e-12
dcl1 7 8 d1
dcl2 9 7 d1
vcl1 99 8 1.83
vcl2 9 50 1.83
gcm 98 7 poly(2) 98 0 30 0 0 1e-5 1e-5
* second pole *
epole 14 98 7 98 1
rpole 14 15 1
cpole 15 98 2e-10
* reference stage *
eref 98 0 poly(2) 99 0 50 0 0 0.5 0.5
ecmref 30 0 poly(2) 1 0 2 0 0 0.5 0.5
* vnoise stage *
rnoise1 19 98 4.6e-3
vnoise1 19 98 0
vnoise2 21 98 0.53
dnoise1 21 19 dn
fnoise1 20 98 vnoise1 1
rnoise2 20 98 1
* inoise stage *
rnoise3 22 98 8.18e-6
vnoise3 22 98 0
vnoise4 24 98 0.575
dnoise2 24 22 dn
fnoise2 23 98 vnoise3 1
rnoise4 23 98 1
* buffer stage *
gbuf 98 13 15 98 1e-2
rbuf 98 13 1e2
* output current reflected to supplies *
fcurr 98 40 voc 1
vcur1 26 98 0
vcur2 98 27 0
dcur1 40 26 d1
dcur2 27 40 d1
* output stage *
vo1 99 90 0
vo2 91 50 0
fout1 0 99 poly(2) vo1 vcur1 -9.27e-3 1 -1
fout2 50 0 poly(2) vo2 vcur2 -9.27e-3 1 -1
gout1 90 10 13 99 0.5
gout2 91 10 13 50 0.5
rout1 10 90 2
rout2 10 91 2
voc 10 28 0
rout3 28 98 1e6
dcl3 13 11 d1
dcl4 12 13 d1
vcl3 11 10 -0.445
vcl4 10 12 -0.445
.model qp1 pnp()
.model qp2 pnp()
.model qn1 npn()
.model qn2 npn()
.model d1 d()
.model dn d(af=1 kf=1e-8)
.ends
R6 1 Vout1 250
C3 1 0 1.5pF
V3 VU1in- Vinput DC 0V