add ads for qa test
This commit is contained in:
dwarning
parent
3942fc48ce
commit
7a41174b5e
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@ -0,0 +1,686 @@
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#
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# ads DC, AC and noise test routines
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#
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#
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# Rel Date Who Comments
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# ==== ========== ============= ========
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# 1.3 06/21/07 Colin McAndrew Verilog-A model support added
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# 1.2 06/30/06 Colin McAndrew Floating node support added
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# Noise simulation added
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# 1.0 04/13/06 Rick Poore/ Initial version
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# Colin McAndrew
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#
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package simulate;
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$simulatorCommand="adssim";
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$netlistFile="adsCkt";
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$mFactorVerilogaName="m"; # for LRM2.1
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#$mFactorVerilogaName="_M"; # for LRM2.2
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use strict;
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sub version {
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my($version,@Field);
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if (!open(SIMULATE,"$simulate::simulatorCommand -version 2>/dev/null|")) {
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die("ERROR: cannot run $main::simulatorName, stopped");
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}
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$version="unknown";
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while (<SIMULATE>) {
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chomp;s/^\s+//;s/\s+$//;
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if (/HPEESOFSIM/i) {
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@Field=split;
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$version=$Field[2];
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}
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}
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close(SIMULATE);
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if (! $main::debug) {
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unlink($simulate::netlistFile);
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}
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return($version);
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}
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sub runNoiseTest {
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my($variant,$outputFile)=@_;
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my($i,@Field,$arg,$name,$value,$type,$pin,$noisePin);
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my(@BiasList,$realVal,$imagVal);
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my($start,$stop,$step,$sign,$inResults,%Index,$iVariables);
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my(@X,@Noise,$temperature,$biasVoltage,$sweepVoltage);
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my(@realAdsResults,@imagAdsResults);
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#
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# Make up the netlist, using a subckt to encapsulate the
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# instance. This simplifies handling of the variants as
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# the actual instance is driven by voltage-controlled
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# voltage sources from the subckt pins, and the currents
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# are fed back to the subckt pins using current-controlled
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# current sources. Pin swapping, polarity reversal, and
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# m-factor scaling can all be handled by simple modifications
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# of this subckt.
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#
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@X=();@Noise=();
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$noisePin=$main::Outputs[0];
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($start,$stop,$step)=split(/\s+/,$main::biasSweepSpec);
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foreach $temperature (@main::Temperature) {
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foreach $biasVoltage (split(/\s+/,$main::biasListSpec)) {
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if ($main::fMin == $main::fMax) {
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push(@X,@main::BiasSweepList);
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}
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if (!open(OF,">$simulate::netlistFile")) {
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die("ERROR: cannot open file $simulate::netlistFile, stopped");
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}
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print OF "; Noise simulation for $main::simulatorName";
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print OF "Options UseNutmegFormat=yes ASCII_Rawfile=yes";
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print OF "Options Temp=$temperature";
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print OF "Vsweep = 0 V";
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&generateCommonNetlistInfo($variant);
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foreach $pin (@main::Pin) {
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if ($main::isFloatingPin{$pin}) {
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print OF "I_Source:i_$pin $pin 0 Idc=0";
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} elsif ($pin eq $main::biasListPin) {
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print OF "V_Source:v_$pin $pin 0 Vdc=$biasVoltage";
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} elsif ($pin eq $main::biasSweepPin) {
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if ($stop < $start) { # flip polarity as ADS always does lo->hi sweep
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print OF "V_Source:v_$pin 0 $pin Vdc=Vsweep";
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} else {
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print OF "V_Source:v_$pin $pin 0 Vdc=Vsweep";
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}
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} else {
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print OF "V_Source:v_$pin $pin 0 Vdc=$main::BiasFor{$pin}";
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}
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}
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print OF "mysub:x_$noisePin ".join(" ",@main::Pin);
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print OF "SDD:fn_$noisePin 0 n_$noisePin I[1,0]=_c1 C[1]=\"v_$noisePin\"";
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print OF "R:r_$noisePin n_$noisePin 0 R=1 Noise=no";
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print OF "OutputPlan:noiseOutput Type=\"Output\"";
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if ($main::fType eq "lin") {
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print OF "SweepPlan:noisePlan Start=$main::fMin Stop=$main::fMax Lin=$main::fSteps";
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} elsif ($main::fType eq "dec") {
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print OF "SweepPlan:noisePlan Start=$main::fMin Stop=$main::fMax Dec=$main::fSteps";
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} else { # octal sweep
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print OF "SweepPlan:noisePlan Start=$main::fMin Stop=$main::fMax Dec=".(int($main::fSteps*log(10)/log(2)));
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}
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if ($stop < $start) {
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$sign=-1;
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print OF "SweepPlan:dcPlan Start=".(-1)*$start." Stop=".(-1)*$stop." Step=".(-1)*$step;
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} else {
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$sign=1;
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print OF "SweepPlan:dcPlan Start=$start Stop=$stop Step=$step";
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}
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print OF "AC:AC1 CalcNoise=yes OutputPlan=\"noiseOutput\" SweepVar=\"freq\" \\";
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print OF "SweepPlan=\"noisePlan\" NoiseNode=\"n_$noisePin\"";
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print OF "ParamSweep:Vsweep SimInstanceName=\"AC1\" SweepVar=\"Vsweep\" SweepPlan=\"dcPlan\"";
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close(OF);
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#
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# Run simulations and get the results
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#
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if (!open(SIMULATE,"$simulate::simulatorCommand $simulate::netlistFile 2>/dev/null |")) {
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die("ERROR: cannot run $main::simulatorName, stopped");
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}
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$inResults=0;
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while (<SIMULATE>) {
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chomp;
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}
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close(SIMULATE);
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if (!open(SIMULATE,"spectra.raw")) {
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die("ERROR: cannot open ADS spectra.raw file, stopped");
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}
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while (<SIMULATE>) {
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chomp;s/^\s+//;s/\s+$//;
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next if (/^$/);
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if (/Plotname:\s*AC/) {
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$inResults=0;next;
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}
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if (/Plotname:\s*CT/) {
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while (<SIMULATE>) {
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chomp;s/^\s+//;s/\s+$//;
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last if (/^$/);
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}
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next;
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}
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if (s/^Variables:\s*//) {
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$iVariables=0;
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@Field=split;
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$Index{$Field[1]}=$Field[0];
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while (<SIMULATE>) {
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chomp;s/^\s+//;s/\s+$//;
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if (/^Values:/) {
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$inResults=1;last;
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}
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++$iVariables;
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@Field=split;
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$Index{$Field[1]}=$Field[0];
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}
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@realAdsResults=();@imagAdsResults=();
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next;
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}
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next if (!$inResults);
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s/,/ /;
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@Field=split;
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shift(@Field) if ($#Field == 2);
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push(@realAdsResults,$Field[0]);
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push(@imagAdsResults,$Field[1]);
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if ($#realAdsResults == $iVariables) {
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if ($main::fMin != $main::fMax) {
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push(@X,1*$realAdsResults[$Index{"freq"}]);
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}
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push(@Noise,$realAdsResults[$Index{"n_$noisePin.noise"}]**2);
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@realAdsResults=();@imagAdsResults=();
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}
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}
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close(SIMULATE);
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}
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}
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#
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# Write the results to a file
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#
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if (!open(OF,">$outputFile")) {
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die("ERROR: cannot open file $outputFile, stopped");
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}
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if ($main::fMin == $main::fMax) {
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printf OF ("V($main::biasSweepPin)");
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} else {
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printf OF ("Freq");
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}
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foreach (@main::Outputs) {
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printf OF (" N($_)");
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}
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printf OF ("\n");
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for ($i=0;$i<=$#X;++$i) {
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if (defined($Noise[$i])) {printf OF ("$X[$i] $Noise[$i]\n")}
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}
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close(OF);
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#
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# Clean up, unless the debug flag was specified
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#
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if (! $main::debug) {
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unlink($simulate::netlistFile);
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unlink("$simulate::netlistFile.ds");
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unlink(".spiceinit");
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unlink("spectra.raw");
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}
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}
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sub runAcTest {
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my($variant,$outputFile)=@_;
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my($i,@Field,$arg,$name,$value,$type,$pin,$mPin,$fPin,%NextPin);
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my(@BiasList,$acStim,$realVal,$imagVal);
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my($start,$stop,$step,$sign,$inResults,%Index,$iVariables);
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my(@X,$omega,%g,%c,$temperature,$biasVoltage,$sweepVoltage,$twoPi);
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my(@realAdsResults,@imagAdsResults,$outputLine);
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$twoPi=8.0*atan2(1.0,1.0);
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#
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# Make up the netlist, using a subckt to encapsulate the
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# instance. This simplifies handling of the variants as
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# the actual instance is driven by voltage-controlled
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# voltage sources from the subckt pins, and the currents
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# are fed back to the subckt pins using current-controlled
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# current sources. Pin swapping, polarity reversal, and
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# m-factor scaling can all be handled by simple modifications
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# of this subckt.
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#
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foreach $mPin (@main::Pin) {
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foreach $fPin (@main::Pin) {
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@{$g{$mPin,$fPin}}=();
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@{$c{$mPin,$fPin}}=();
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}
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}
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@X=();
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($start,$stop,$step)=split(/\s+/,$main::biasSweepSpec);
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foreach $temperature (@main::Temperature) {
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foreach $biasVoltage (split(/\s+/,$main::biasListSpec)) {
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if ($main::fMin == $main::fMax) {
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push(@X,@main::BiasSweepList);
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}
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if (!open(OF,">$simulate::netlistFile")) {
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die("ERROR: cannot open file $simulate::netlistFile, stopped");
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}
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print OF "; AC simulation for $main::simulatorName";
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print OF "Options UseNutmegFormat=yes ASCII_Rawfile=yes";
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print OF "Options Temp=$temperature";
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print OF "Vsweep = 0 V";
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&generateCommonNetlistInfo($variant);
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foreach $fPin (@main::Pin) {
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foreach $mPin (@main::Pin) {
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if ($mPin eq $fPin) {
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$acStim=" Vac=1";
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} else {
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$acStim="";
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}
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if ($main::isFloatingPin{$mPin}) {
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print OF "I_Source:i_${mPin}_$fPin ${mPin}_$fPin 0 Idc=0";
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} elsif ($mPin eq $main::biasListPin) {
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print OF "V_Source:v_${mPin}_$fPin ${mPin}_$fPin 0 Vdc=$biasVoltage$acStim";
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} elsif ($mPin eq $main::biasSweepPin) {
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if ($stop < $start) { # flip polarity as ADS always does lo->hi sweep
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$acStim=~s/1/-1/;
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print OF "V_Source:v_${mPin}_$fPin 0 ${mPin}_$fPin Vdc=Vsweep$acStim";
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} else {
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print OF "V_Source:v_${mPin}_$fPin ${mPin}_$fPin 0 Vdc=Vsweep$acStim";
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}
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} else {
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print OF "V_Source:v_${mPin}_$fPin ${mPin}_$fPin 0 Vdc=$main::BiasFor{$mPin}$acStim";
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}
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}
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print OF "mysub:x_$fPin ".join("_$fPin ",@main::Pin)."_$fPin ";
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}
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if ($main::fType eq "lin") {
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print OF "SweepPlan:acPlan Start=$main::fMin Stop=$main::fMax Lin=$main::fSteps";
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} elsif ($main::fType eq "dec") {
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print OF "SweepPlan:acPlan Start=$main::fMin Stop=$main::fMax Dec=$main::fSteps";
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} else { # octal sweep
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print OF "SweepPlan:acPlan Start=$main::fMin Stop=$main::fMax Dec=".(int($main::fSteps*log(10)/log(2)));
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}
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if ($stop < $start) {
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$sign=-1;
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print OF "SweepPlan:dcPlan Start=".(-1)*$start." Stop=".(-1)*$stop." Step=".(-1)*$step;
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} else {
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$sign=1;
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print OF "SweepPlan:dcPlan Start=$start Stop=$stop Step=$step";
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}
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print OF "OutputPlan:acOutput Type=\"Output\" UseNodeNestLevel=yes NodeNestLevel=2 UseEquationNestLevel=yes EquationNestLevel=2";
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print OF "AC:AC1 OutputPlan=\"acOutput\" SweepVar=\"freq\" SweepPlan=\"acPlan\"";
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print OF "ParamSweep:Vsweep SimInstanceName=\"AC1\" SweepVar=\"Vsweep\" SweepPlan=\"dcPlan\"";
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close(OF);
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#
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# Run simulations and get the results
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#
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if (!open(SIMULATE,"$simulate::simulatorCommand $simulate::netlistFile 2>/dev/null |")) {
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die("ERROR: cannot run $main::simulatorName, stopped");
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}
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$inResults=0;
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while (<SIMULATE>) {
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chomp;
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}
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close(SIMULATE);
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if (!open(SIMULATE,"spectra.raw")) {
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die("ERROR: cannot open ADS spectra.raw file, stopped");
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}
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while (<SIMULATE>) {
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chomp;s/^\s+//;s/\s+$//;
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next if (/^$/);
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if (/Plotname:\s*AC/) {
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$inResults=0;next;
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}
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if (/Plotname:\s*CT/) {
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while (<SIMULATE>) {
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chomp;s/^\s+//;s/\s+$//;
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last if (/^$/);
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}
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next;
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}
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if (s/^Variables:\s*//) {
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$iVariables=0;
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@Field=split;
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$Index{$Field[1]}=$Field[0];
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while (<SIMULATE>) {
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chomp;s/^\s+//;s/\s+$//;
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if (/^Values:/) {
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$inResults=1;last;
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}
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++$iVariables;
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@Field=split;
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$Index{$Field[1]}=$Field[0];
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}
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@realAdsResults=();@imagAdsResults=();
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next;
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}
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next if (!$inResults);
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s/,/ /;
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@Field=split;
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shift(@Field) if ($#Field == 2);
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push(@realAdsResults,$Field[0]);
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push(@imagAdsResults,$Field[1]);
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if ($#realAdsResults == $iVariables) {
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if ($main::fMin != $main::fMax) {
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push(@X,1*$realAdsResults[$Index{"freq"}]);
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}
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$omega=$twoPi*$realAdsResults[$Index{"freq"}];
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foreach (@main::Outputs) {
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($type,$mPin,$fPin)=split(/\s+/,$_);
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push(@{$g{$mPin,$fPin}},1*$realAdsResults[$Index{"v_${mPin}_${fPin}.i"}]);
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if ($mPin eq $fPin) {
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push(@{$c{$mPin,$fPin}},$imagAdsResults[$Index{"v_${mPin}_${fPin}.i"}]/$omega);
|
||||||
|
} else {
|
||||||
|
push(@{$c{$mPin,$fPin}},-1*$imagAdsResults[$Index{"v_${mPin}_${fPin}.i"}]/$omega);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
@realAdsResults=();@imagAdsResults=();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
close(SIMULATE);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#
|
||||||
|
# Write the results to a file
|
||||||
|
#
|
||||||
|
|
||||||
|
if (!open(OF,">$outputFile")) {
|
||||||
|
die("ERROR: cannot open file $outputFile, stopped");
|
||||||
|
}
|
||||||
|
if ($main::fMin == $main::fMax) {
|
||||||
|
printf OF ("V($main::biasSweepPin)");
|
||||||
|
} else {
|
||||||
|
printf OF ("Freq");
|
||||||
|
}
|
||||||
|
foreach (@main::Outputs) {
|
||||||
|
($type,$mPin,$fPin)=split(/\s+/,$_);
|
||||||
|
printf OF (" $type($mPin,$fPin)");
|
||||||
|
}
|
||||||
|
printf OF ("\n");
|
||||||
|
for ($i=0;$i<=$#X;++$i) {
|
||||||
|
$outputLine="$X[$i]";
|
||||||
|
foreach (@main::Outputs) {
|
||||||
|
($type,$mPin,$fPin)=split(/\s+/,$_);
|
||||||
|
if ($type eq "g") {
|
||||||
|
if (defined(${$g{$mPin,$fPin}}[$i])) {
|
||||||
|
$outputLine.=" ${$g{$mPin,$fPin}}[$i]";
|
||||||
|
} else {
|
||||||
|
undef($outputLine);last;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
if (defined(${$c{$mPin,$fPin}}[$i])) {
|
||||||
|
$outputLine.=" ${$c{$mPin,$fPin}}[$i]";
|
||||||
|
} else {
|
||||||
|
undef($outputLine);last;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (defined($outputLine)) {printf OF ("$outputLine\n")}
|
||||||
|
}
|
||||||
|
close(OF);
|
||||||
|
|
||||||
|
#
|
||||||
|
# Clean up, unless the debug flag was specified
|
||||||
|
#
|
||||||
|
|
||||||
|
if (! $main::debug) {
|
||||||
|
unlink($simulate::netlistFile);
|
||||||
|
unlink("$simulate::netlistFile.ds");
|
||||||
|
unlink(".spiceinit");
|
||||||
|
unlink("spectra.raw");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
sub runDcTest {
|
||||||
|
my($variant,$outputFile)=@_;
|
||||||
|
my($i,$arg,$name,$value,$pin);
|
||||||
|
my($start,$stop,$step);
|
||||||
|
my(@V,%DC,$temperature,$biasVoltage);
|
||||||
|
my($inData,$inResults,$iVariables,@Field,%Index,@AdsResults,$sign);
|
||||||
|
|
||||||
|
if (!defined($main::biasSweepPin)) {
|
||||||
|
die("ERROR: biasSweep must be specified for a DC I(V) test, stopped");
|
||||||
|
}
|
||||||
|
|
||||||
|
#
|
||||||
|
# Make up the netlist, using a subckt to encapsulate the
|
||||||
|
# instance. This simplifies handling of the variants as
|
||||||
|
# the actual instance is driven by voltage-controlled
|
||||||
|
# voltage sources from the subckt pins, and the currents
|
||||||
|
# are fed back to the subckt pins using current-controlled
|
||||||
|
# current sources. Pin swapping, polarity reversal, and
|
||||||
|
# m-factor scaling can all be handled by simple modifications
|
||||||
|
# of this subckt.
|
||||||
|
#
|
||||||
|
|
||||||
|
@V=();
|
||||||
|
foreach $pin (@main::Outputs) {@{$DC{$pin}}=()}
|
||||||
|
($start,$stop,$step)=split(/\s+/,$main::biasSweepSpec);
|
||||||
|
$start-=$step;
|
||||||
|
foreach $temperature (@main::Temperature) {
|
||||||
|
foreach $biasVoltage (split(/\s+/,$main::biasListSpec)) {
|
||||||
|
if (!open(OF,">$simulate::netlistFile")) {
|
||||||
|
die("ERROR: cannot open file $simulate::netlistFile, stopped");
|
||||||
|
}
|
||||||
|
print OF "; DC simulation for $main::simulatorName";
|
||||||
|
print OF "Options UseNutmegFormat=yes ASCII_Rawfile=yes";
|
||||||
|
print OF "Options Temp=$temperature";
|
||||||
|
&generateCommonNetlistInfo($variant);
|
||||||
|
foreach $pin (@main::Pin) {
|
||||||
|
if ($main::isFloatingPin{$pin}) {
|
||||||
|
print OF "I_Source:i_$pin $pin 0 Idc=0";
|
||||||
|
} elsif ($pin eq $main::biasListPin) {
|
||||||
|
print OF "V_Source:v_$pin $pin 0 Vdc=$biasVoltage";
|
||||||
|
} elsif ($pin eq $main::biasSweepPin) {
|
||||||
|
if ($stop < $start) { # flip polarity as ADS always does lo->hi sweep
|
||||||
|
print OF "V_Source:v_$pin 0 $pin Vdc=".(-1)*$start;
|
||||||
|
} else {
|
||||||
|
print OF "V_Source:v_$pin $pin 0 Vdc=$start";
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
print OF "V_Source:v_$pin $pin 0 Vdc=$main::BiasFor{$pin}";
|
||||||
|
}
|
||||||
|
}
|
||||||
|
print OF "mysub:x1 ".join(" ",@main::Pin);
|
||||||
|
if ($stop < $start) {
|
||||||
|
$sign=-1;
|
||||||
|
print OF "SweepPlan:dcPlan Start=".(-1)*$start." Stop=".(-1)*$stop." Step=".(-1)*$step;
|
||||||
|
} else {
|
||||||
|
$sign=1;
|
||||||
|
print OF "SweepPlan:dcPlan Start=$start Stop=$stop Step=$step";
|
||||||
|
}
|
||||||
|
print OF "DC:DC1 SweepVar=\"v_$main::biasSweepPin.Vdc\" SweepPlan=\"dcPlan\"";
|
||||||
|
close(OF);
|
||||||
|
|
||||||
|
#
|
||||||
|
# Run simulations and get the results
|
||||||
|
#
|
||||||
|
|
||||||
|
if (!open(SIMULATE,"$simulate::simulatorCommand $simulate::netlistFile 2>/dev/null |")) {
|
||||||
|
die("ERROR: cannot run $main::simulatorName, stopped");
|
||||||
|
}
|
||||||
|
$inResults=0;
|
||||||
|
while (<SIMULATE>) {
|
||||||
|
chomp;
|
||||||
|
}
|
||||||
|
close(SIMULATE);
|
||||||
|
if (!open(SIMULATE,"spectra.raw")) {
|
||||||
|
die("ERROR: cannot open ADS spectra.raw file, stopped");
|
||||||
|
}
|
||||||
|
while (<SIMULATE>) {
|
||||||
|
chomp;s/^\s+//;s/\s+$//;
|
||||||
|
if (s/^Variables:\s*//) {
|
||||||
|
$iVariables=0;
|
||||||
|
@Field=split;
|
||||||
|
$Index{$Field[1]}=$Field[0];
|
||||||
|
while (<SIMULATE>) {
|
||||||
|
chomp;s/^\s+//;s/\s+$//;
|
||||||
|
if (/^Values:/) {
|
||||||
|
$inResults=1;last;
|
||||||
|
}
|
||||||
|
++$iVariables;
|
||||||
|
@Field=split;
|
||||||
|
$Index{$Field[1]}=$Field[0];
|
||||||
|
}
|
||||||
|
@AdsResults=();
|
||||||
|
next;
|
||||||
|
}
|
||||||
|
next if (!$inResults);
|
||||||
|
@Field=split;
|
||||||
|
shift(@Field) if ($#Field == 2);
|
||||||
|
push(@AdsResults,@Field);
|
||||||
|
if ($#AdsResults == $iVariables) {
|
||||||
|
push(@V,$sign*$AdsResults[$Index{"v_$main::biasSweepPin.Vdc"}]);
|
||||||
|
foreach $pin (@main::Outputs) {
|
||||||
|
if ($pin eq $main::biasSweepPin) {
|
||||||
|
push(@{$DC{$pin}},$sign*$AdsResults[$Index{"v_$pin.i"}]);
|
||||||
|
} elsif ($main::isFloatingPin{$pin}) {
|
||||||
|
push(@{$DC{$pin}},1*$AdsResults[$Index{"$pin"}]);
|
||||||
|
} else {
|
||||||
|
push(@{$DC{$pin}},1*$AdsResults[$Index{"v_$pin.i"}]);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
@AdsResults=();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
close(SIMULATE);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#
|
||||||
|
# Write the results to a file
|
||||||
|
#
|
||||||
|
|
||||||
|
if (!open(OF,">$outputFile")) {
|
||||||
|
die("ERROR: cannot open file $outputFile, stopped");
|
||||||
|
}
|
||||||
|
printf OF ("V($main::biasSweepPin)");
|
||||||
|
foreach $pin (@main::Outputs) {
|
||||||
|
if ($main::isFloatingPin{$pin}) {
|
||||||
|
printf OF (" V($pin)");
|
||||||
|
} else {
|
||||||
|
printf OF (" I($pin)");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
printf OF ("\n");
|
||||||
|
for ($i=0;$i<=$#V;++$i) {
|
||||||
|
next if (abs($V[$i]-$start) < abs(0.1*$step)); # this is dummy first bias point
|
||||||
|
printf OF ("$V[$i]");
|
||||||
|
foreach $pin (@main::Outputs) {printf OF (" ${$DC{$pin}}[$i]")}
|
||||||
|
printf OF ("\n");
|
||||||
|
}
|
||||||
|
close(OF);
|
||||||
|
|
||||||
|
#
|
||||||
|
# Clean up, unless the debug flag was specified
|
||||||
|
#
|
||||||
|
|
||||||
|
if (! $main::debug) {
|
||||||
|
unlink($simulate::netlistFile);
|
||||||
|
unlink("$simulate::netlistFile.ds");
|
||||||
|
unlink(".spiceinit");
|
||||||
|
unlink("spectra.raw");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
sub generateCommonNetlistInfo {
|
||||||
|
my($variant)=$_[0];
|
||||||
|
my(@Pin_x,$arg,$name,$value,$eFactor,$fFactor,$pin,@Args);
|
||||||
|
foreach $pin (@main::Pin) {push(@Pin_x,"${pin}_x")}
|
||||||
|
if ($variant=~/^scale$/) {
|
||||||
|
die("ERROR: there is no scale or shrink option for ads, stopped");
|
||||||
|
}
|
||||||
|
if ($variant=~/^shrink$/) {
|
||||||
|
die("ERROR: there is no scale or shrink option for ads, stopped");
|
||||||
|
}
|
||||||
|
if ($variant=~/_P/) {
|
||||||
|
$eFactor=-1;$fFactor=1;
|
||||||
|
} else {
|
||||||
|
$eFactor=1;$fFactor=-1;
|
||||||
|
}
|
||||||
|
if ($variant=~/^m$/) {
|
||||||
|
if ($main::outputNoise) {
|
||||||
|
$fFactor/=sqrt($main::mFactor);
|
||||||
|
} else {
|
||||||
|
$fFactor/=$main::mFactor;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (defined($main::verilogaFile)) {
|
||||||
|
print OF "";
|
||||||
|
print OF "#load \"veriloga\", \"$main::verilogaFile\";";
|
||||||
|
}
|
||||||
|
print OF " ";
|
||||||
|
print OF "define mysub (".join(" ",@Pin_x).")";
|
||||||
|
foreach $pin (@main::Pin) {
|
||||||
|
if ($main::isFloatingPin{$pin}) { # assumed "dt" thermal pin, no scaling sign change
|
||||||
|
print OF "V_Source:v_$pin ${pin} ${pin}_x Vdc=0";
|
||||||
|
} elsif ($variant=~/^Flip/ && defined($main::flipPin{$pin})) {
|
||||||
|
print OF "#uselib \"ckt\", \"VCVS\"";
|
||||||
|
print OF "VCVS:e_$pin $main::flipPin{$pin}_x 0 ${pin}_v 0 G=$eFactor";
|
||||||
|
print OF "V_Source:v_$pin ${pin}_v ${pin} Vdc=0";
|
||||||
|
print OF "SDD:f_$pin $main::flipPin{$pin}_x 0 C[1]=\"v_$pin\" I[1]=_c1*$fFactor";
|
||||||
|
} else {
|
||||||
|
print OF "#uselib \"ckt\", \"VCVS\"";
|
||||||
|
print OF "VCVS:e_$pin ${pin}_x 0 ${pin}_v 0 G=$eFactor";
|
||||||
|
print OF "V_Source:v_$pin ${pin}_v ${pin} Vdc=0";
|
||||||
|
print OF "SDD:f_$pin ${pin}_x 0 C[1]=\"v_$pin\" I[1]=_c1*$fFactor";
|
||||||
|
}
|
||||||
|
}
|
||||||
|
print OF " ";
|
||||||
|
if (defined($main::verilogaFile)) {
|
||||||
|
if ($variant=~/_P/) {
|
||||||
|
@Args=split(/\s+/,$main::pTypeSelectionArguments);
|
||||||
|
} else {
|
||||||
|
@Args=split(/\s+/,$main::nTypeSelectionArguments);
|
||||||
|
}
|
||||||
|
print OF "$Args[0]:${main::keyLetter}1 ".join(" ",@main::Pin)." \\";
|
||||||
|
foreach $arg (@Args[1..$#Args]) {
|
||||||
|
($name,$value)=split(/=/,$arg);
|
||||||
|
print OF " ".$name."=$value \\";
|
||||||
|
}
|
||||||
|
foreach $arg (@main::InstanceParameters) {
|
||||||
|
($name,$value)=split(/=/,$arg);
|
||||||
|
if ($variant=~/^scale$/) {
|
||||||
|
if ($main::isLinearScale{$name}) {
|
||||||
|
$value/=$main::scaleFactor;
|
||||||
|
} elsif ($main::isAreaScale{$name}) {
|
||||||
|
$value/=$main::scaleFactor**2;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if ($variant=~/^shrink$/) {
|
||||||
|
if ($main::isLinearScale{$name}) {
|
||||||
|
$value/=(1.0-$main::shrinkPercent*0.01);
|
||||||
|
} elsif ($main::isAreaScale{$name}) {
|
||||||
|
$value/=(1.0-$main::shrinkPercent*0.01)**2;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
print OF " ".$name."=$value \\";
|
||||||
|
}
|
||||||
|
if ($variant eq "m") {
|
||||||
|
print OF " $simulate::mFactorVerilogaName=$main::mFactor \\";
|
||||||
|
}
|
||||||
|
foreach $arg (@main::ModelParameters) {
|
||||||
|
print OF " ".$arg." \\";
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
print OF "mymodel:${main::keyLetter}1 ".join(" ",@main::Pin)." \\";
|
||||||
|
foreach $arg (@main::InstanceParameters) {
|
||||||
|
($name,$value)=split(/=/,$arg);
|
||||||
|
if ($variant=~/^scale$/) {
|
||||||
|
if ($main::isLinearScale{$name}) {
|
||||||
|
$value/=$main::scaleFactor;
|
||||||
|
} elsif ($main::isAreaScale{$name}) {
|
||||||
|
$value/=$main::scaleFactor**2;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if ($variant=~/^shrink$/) {
|
||||||
|
if ($main::isLinearScale{$name}) {
|
||||||
|
$value/=(1.0-$main::shrinkPercent*0.01);
|
||||||
|
} elsif ($main::isAreaScale{$name}) {
|
||||||
|
$value/=(1.0-$main::shrinkPercent*0.01)**2;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
print OF " ".ucfirst($name)."=$value \\";
|
||||||
|
}
|
||||||
|
if ($variant eq "m") {
|
||||||
|
print OF " _M=$main::mFactor \\";
|
||||||
|
}
|
||||||
|
print OF " ";
|
||||||
|
if ($variant=~/_P/) {
|
||||||
|
print OF "model mymodel $main::pTypeSelectionArguments \\";
|
||||||
|
} else {
|
||||||
|
print OF "model mymodel $main::nTypeSelectionArguments \\";
|
||||||
|
}
|
||||||
|
foreach $arg (@main::ModelParameters) {
|
||||||
|
print OF " ".ucfirst($arg)." \\";
|
||||||
|
}
|
||||||
|
}
|
||||||
|
print OF " ";
|
||||||
|
print OF "end mysub";
|
||||||
|
print OF " ";
|
||||||
|
}
|
||||||
|
|
||||||
|
1;
|
||||||
|
|
@ -32,6 +32,8 @@ help() {
|
||||||
|
|
||||||
hspice run tests and compare results hspice
|
hspice run tests and compare results hspice
|
||||||
|
|
||||||
|
ads run tests and compare results ads
|
||||||
|
|
||||||
clean remove all previously generated simulation results
|
clean remove all previously generated simulation results
|
||||||
|
|
||||||
NOTE: if test results exist they are not resimulated
|
NOTE: if test results exist they are not resimulated
|
||||||
|
|
@ -126,6 +128,10 @@ hspice() {
|
||||||
run_test hspice
|
run_test hspice
|
||||||
}
|
}
|
||||||
|
|
||||||
|
ads() {
|
||||||
|
run_test ads
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
#####
|
#####
|
||||||
##### clean
|
##### clean
|
||||||
|
|
@ -134,6 +140,7 @@ hspice() {
|
||||||
clean() {
|
clean() {
|
||||||
rm -rf ${qaResultsDirectory}/ngspice ngspiceCkt*
|
rm -rf ${qaResultsDirectory}/ngspice ngspiceCkt*
|
||||||
rm -rf ${qaResultsDirectory}/hspice hspiceCkt*
|
rm -rf ${qaResultsDirectory}/hspice hspiceCkt*
|
||||||
|
rm -rf ${qaResultsDirectory}/ads adsCkt*
|
||||||
}
|
}
|
||||||
|
|
||||||
clean_ngspice() {
|
clean_ngspice() {
|
||||||
|
|
@ -144,9 +151,13 @@ clean_hspice() {
|
||||||
rm -rf ${qaResultsDirectory}/hspice hspiceCkt*
|
rm -rf ${qaResultsDirectory}/hspice hspiceCkt*
|
||||||
}
|
}
|
||||||
|
|
||||||
|
clean_ads() {
|
||||||
|
rm -rf ${qaResultsDirectory}/ads adsCkt*
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
all() {
|
all() {
|
||||||
ngspice hspice
|
ngspice hspice ads
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -172,7 +183,7 @@ done
|
||||||
|
|
||||||
for arg in $@ ; do
|
for arg in $@ ; do
|
||||||
case "$arg" in
|
case "$arg" in
|
||||||
all | clean | clean_ngspice | ngspice | clean_hspice | hspice)
|
all | clean | clean_ngspice | ngspice | clean_hspice | hspice | clean_ads | ads)
|
||||||
"$arg"
|
"$arg"
|
||||||
;;
|
;;
|
||||||
*)
|
*)
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue