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correct init for convergence test

This commit is contained in:
dwarning 2019-03-07 23:29:09 +01:00 committed by Holger Vogt
parent 3494e6b390
commit 7966aa36ae
1 changed files with 1 additions and 1 deletions
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2
src/spicelib/devices/vbic/vbicload.c
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@ -739,7 +739,7 @@ VBICload(GENmodel *inModel, CKTcircuit *ckt)
/* /*
* limit nonlinear branch voltages * limit nonlinear branch voltages
*/ */
ichk1 = 1; ichk1 = 1, ichk2 = 1, ichk3 = 1, ichk4 = 1, ichk5 = 1;
Vbei = DEVpnjlim(Vbei,*(ckt->CKTstate0 + here->VBICvbei),vt, Vbei = DEVpnjlim(Vbei,*(ckt->CKTstate0 + here->VBICvbei),vt,
here->VBICtVcrit,&icheck); here->VBICtVcrit,&icheck);
Vbex = DEVpnjlim(Vbex,*(ckt->CKTstate0 + here->VBICvbex),vt, Vbex = DEVpnjlim(Vbex,*(ckt->CKTstate0 + here->VBICvbex),vt,