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V Pulse delivers erratic outputs, when not parameterized properly. 

Update the pulse generation: negative TR, TF, PW, PER not possible,
get default values instead. 0 PW is allowed.

Defaults are:
TR negative or 0 --> TR = ckt->CKTstep
TF negative or 0 --> TF = ckt->CKTstep
PW < 0 --> PW = 0
PER <= 0 --> PER = TR + TF + PW */
This commit is contained in:
Holger Vogt 2026-02-21 14:20:30 +01:00
parent 527cc86969
commit 7159d6aa4b
2 changed files with 22 additions and 13 deletions
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16
src/spicelib/devices/vsrc/vsrcacct.c
View File

@ -56,20 +56,24 @@ VSRCaccept(CKTcircuit *ckt, GENmodel *inModel)
double phase;
double deltat;
/* TR negative or 0 --> TR = ckt->CKTstep
TF negative or 0 --> TF = ckt->CKTstep
PW < 0 --> PW = 0
PER <= 0 --> PER = TR + TF + PW */
TD = here->VSRCfunctionOrder > 2
? here->VSRCcoeffs[2] : 0.0;
TR = here->VSRCfunctionOrder > 3
&& here->VSRCcoeffs[3] != 0.0
&& here->VSRCcoeffs[3] > 0.0
? here->VSRCcoeffs[3] : ckt->CKTstep;
TF = here->VSRCfunctionOrder > 4
&& here->VSRCcoeffs[4] != 0.0
&& here->VSRCcoeffs[4] > 0.0
? here->VSRCcoeffs[4] : ckt->CKTstep;
PW = here->VSRCfunctionOrder > 5
&& here->VSRCcoeffs[5] != 0.0
? here->VSRCcoeffs[5] : ckt->CKTfinalTime;
&& here->VSRCcoeffs[5] >= 0.0
? here->VSRCcoeffs[5] : 0.0;
PER = here->VSRCfunctionOrder > 6
&& here->VSRCcoeffs[6] != 0.0
? here->VSRCcoeffs[6] : ckt->CKTfinalTime;
&& here->VSRCcoeffs[6] > 0.0
? here->VSRCcoeffs[6] : TR + TF + PW;
PHASE = here->VSRCfunctionOrder > 7
? here->VSRCcoeffs[7] : 0.0;

19
src/spicelib/devices/vsrc/vsrcload.c
View File

@ -86,7 +86,12 @@ VSRCload(GENmodel *inModel, CKTcircuit *ckt)
} else {
time = ckt->CKTtime;
}
/* use the transient functions */
/* use the transient functions. Parameter limits:
TR negative or 0 --> TR = ckt->CKTstep
TF negative or 0 --> TF = ckt->CKTstep
PW < 0 --> PW = 0
PER <= 0 --> PER = TR + TF + PW
*/
switch(here->VSRCfunctionType) {
default:
@ -106,17 +111,17 @@ VSRCload(GENmodel *inModel, CKTcircuit *ckt)
TD = here->VSRCfunctionOrder > 2
? here->VSRCcoeffs[2] : 0.0;
TR = here->VSRCfunctionOrder > 3
&& here->VSRCcoeffs[3] != 0.0
&& here->VSRCcoeffs[3] > 0.0
? here->VSRCcoeffs[3] : ckt->CKTstep;
TF = here->VSRCfunctionOrder > 4
&& here->VSRCcoeffs[4] != 0.0
&& here->VSRCcoeffs[4] > 0.0
? here->VSRCcoeffs[4] : ckt->CKTstep;
PW = here->VSRCfunctionOrder > 5
&& here->VSRCcoeffs[5] != 0.0
? here->VSRCcoeffs[5] : ckt->CKTfinalTime;
&& here->VSRCcoeffs[5] >= 0.0
? here->VSRCcoeffs[5] : 0.0;
PER = here->VSRCfunctionOrder > 6
&& here->VSRCcoeffs[6] != 0.0
? here->VSRCcoeffs[6] : ckt->CKTfinalTime;
&& here->VSRCcoeffs[6] > 0.0
? here->VSRCcoeffs[6] : TR + TF + PW;
/* shift time by delay time TD */
time -= TD;