parent
d6350ca86d
commit
70b2408f39
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@ -1,5 +1,9 @@
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2009-12-21 Holger Vogt
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* com_measure2.com, measure.c: add vector to the meas command
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* com_measure2.com, measure.c: add vectors to the meas command.
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inpcom.c: no parsing of ternary function in .control section (not
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yet defined anyway).
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/examples/measure /examples/control_structs: new or updated example
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files.
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2009-12-20 Holger Vogt
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* fixing the time 0 value of sine in isrc, vsrc
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@ -0,0 +1,51 @@
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BJT ft Test
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vce 1 0 dc 3.0
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vgain 1 c dc 0.0
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f 0 2 vgain -1000
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l 2 b 1g
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c 2 0 1g
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ib 0 b dc 0.0 ac 1.0
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ic 0 c 0.01
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q1 c b 0 bfs17
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.control
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foreach myic 0.5e-3 1e-3 5e-3 10e-3 50e-3 100e-3
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alter ic = $myic
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ac dec 10 10k 5g
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end
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*foreach mytf 50p 100p 150p 200p 250p 300p
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* altermod q.x1.q1 tf = $mytf
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* ac dec 10 10k 5g
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*end
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plot abs(ac1.vgain#branch) abs(ac2.vgain#branch) abs(ac3.vgain#branch) abs(ac4.vgain#branch) abs(ac5.vgain#branch) abs(ac6.vgain#branch) ylimit 0.1 100 loglog
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.endc
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*****************************************************************
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* SPICE2G6 MODEL OF THE NPN BIPOLAR TRANSISTOR BFS17 (SOT-23) *
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* REV: 98.1 DANALYSE GMBH BERLIN (27.07.1998) *
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*****************************************************************
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.SUBCKT BFS17C 1 2 3
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Q1 6 5 7 BFS17 1.000
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LC 1 6 0.350N
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L1 2 4 0.400N
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LB 4 5 0.500N
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L2 3 8 0.400N
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LE 8 7 0.600N
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CGBC 4 6 70.00F
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CGBE 4 8 0.150P
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CGCE 6 8 15.00F
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.ENDS
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.MODEL BFS17 NPN (level=1 IS=0.480F NF=1.008 BF=99.655 VAF=90.000 IKF=0.190
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+ ISE=7.490F NE=1.762 NR=1.010 BR=38.400 VAR=7.000 IKR=93.200M
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+ ISC=0.200F NC=1.042
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+ RB=1.500 IRB=0.100M RBM=1.200
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+ RE=0.500 RC=2.680
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+ CJE=1.325P VJE=0.700 MJE=0.220 FC=0.890
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+ CJC=1.050P VJC=0.610 MJC=0.240 XCJC=0.400
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+ TF=56.940P TR=1.000N PTF=21.000
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+ XTF=68.398 VTF=0.600 ITF=0.700
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+ XTB=1.600 EG=1.110 XTI=3.000
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+ KF=1.000F AF=1.000)
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.end
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@ -0,0 +1,16 @@
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*test sequence for repeat
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.control
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let loop = 0
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while loop < 4
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let index = 0
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repeat
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let index = index + 1
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if index > 4
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break
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end
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end
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echo
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echo index "$&index" loop "$&loop"
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let loop = loop + 1
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end
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.endc
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@ -0,0 +1,113 @@
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Inverter example circuit
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* This netlist demonstrates the following:
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* global nodes (vdd, gnd)
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* autostop (.tran defines simulation end as 4ns but simulation stops at
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* 142.5ps when .measure statements are evaluated)
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* scale (all device units are in microns)
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* model binning (look in device.values file for which bin chosen)
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*
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* m.x1.mn:
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* model = nch.2
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*
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* m.x1.mp:
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* model = pch.2
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*
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* parameters
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* parameterized subckt
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* vsrc with repeat
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* .measure statements for delay and an example ternary operator
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* device listing and parameter listing
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* You can run the example circuit with this command:
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*
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* ngspice inverter3.sp
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* global nodes
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.global vdd gnd
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* autostop -- stop simulation early if .measure statements done
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* scale -- define scale factor for mosfet device parameters (l,w,area,perimeter)
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*.option autostop
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.option scale = 1e-6
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* model binning
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.model nch.1 nmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=0.1u wmax=10u )
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.model nch.2 nmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=10u wmax=100u )
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.model pch.1 pmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=0.1u wmax=10u )
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.model pch.2 pmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=10u wmax=100u )
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* parameters
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.param vp = 1.0v
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.param lmin = 0.10
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.param wmin = 0.12
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.param plmin = 'lmin'
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.param nlmin = 'lmin'
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.param wpmin = 'wmin'
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.param wnmin = 'wmin'
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.param drise = 400ps
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.param dfall = 100ps
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.param trise = 100ps
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.param tfall = 100ps
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.param period = 1ns
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.param skew_meas = 'vp/2'
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* parameterized subckt
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.subckt inv in out pw='wpmin' pl='plmin' nw='wnmin' nl='nlmin'
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mp out in vdd vdd pch w='pw' l='pl'
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mn out in gnd gnd nch w='nw' l='nl'
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.ends
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v0 vdd gnd 'vp'
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* vsrc with repeat
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v1 in gnd pwl
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+ 0ns 'vp'
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+ 'dfall-0.8*tfall' 'vp'
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+ 'dfall-0.4*tfall' '0.9*vp'
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+ 'dfall+0.4*tfall' '0.1*vp'
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+ 'dfall+0.8*tfall' 0v
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+ 'drise-0.8*trise' 0v
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+ 'drise-0.4*trise' '0.1*vp'
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+ 'drise+0.4*trise' '0.9*vp'
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+ 'drise+0.8*trise' 'vp'
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+ 'period+dfall-0.8*tfall' 'vp'
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+ r='dfall-0.8*tfall'
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x1 in out inv pw=60 nw=20
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c1 out gnd 220fF
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.control
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tran 1ps 4ns
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meas tran inv_delay trig v(in) val=0.5 fall=1 targ v(out) val=0.5 rise=1
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meas tran inv_delay2 trig v(in) val=0.5 td=1n fall=1 targ v(out) val=0.5 rise=1
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meas tran test_data1 trig AT = 1n targ v(out) val=0.5 rise=3
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meas tran out_slew trig v(out) val=0.2 rise=2 targ v(out) val=0.8 rise=2
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*.meas tran delay_chk param='(inv_delay < 100ps) ? 1 : 0'
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if ( inv_delay < 100ps )
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let delay_chk = 1
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else
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let delay_chk = 0
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end
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echo delay_chk = "$&delay_chk"
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meas tran skew when v(out)=0.6
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let skew_meas = 0.5
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meas tran skew2 when v(out)=skew_meas
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meas tran skew3 when v(out)=skew_meas fall=2
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meas tran skew4 when v(out)=skew_meas fall=LAST
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meas tran skew5 FIND v(out) AT=2n
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let dfall = 100p
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let period = 1n
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let delta = dfall+period
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meas tran v0_min min i(v0) from=dfall to=delta
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meas tran i_v0_min min_at i(v0) from=dfall to=delta
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meas tran v0_avg avg i(v0) from = dfall to = delta
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meas tran v0_integ integ i(v0) from=dfall to=delta
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meas tran v0_rms rms i(v0) from=dfall to=delta
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rusage all
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plot v(in) v(out)
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.endc
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.end
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@ -0,0 +1,32 @@
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***** Single NMOS Transistor .measure (Id-Vd) ***
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m1 d g s b nch L=0.6u W=10.0u
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vgs g 0 3.5
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vds d 0 3.5
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vs s 0 dc 0
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vb b 0 dc 0
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* model binning
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.model nch.1 nmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=0.1u wmax=10u )
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.model nch.2 nmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=10u wmax=100u )
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.model pch.1 pmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=0.1u wmax=10u )
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.model pch.2 pmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=10u wmax=100u )
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.control
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dc vds 0 3.5 0.05 vgs 0.5 3.5 0.5
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meas dc is_at FIND i(vs) AT=1
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meas dc is_max max i(vs) from=0 to=3.5
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meas dc vds_at2 when i(vs)=10m
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meas dc vd_diff1 trig i(vs) val=0.005 rise=1 targ i(vs) val=0.01 rise=1
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meas dc vd_diff2 trig i(vs) val=0.005 rise=1 targ i(vs) val=0.01 rise=2
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*rusage all
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plot i(vs)
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.endc
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.end
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@ -18,21 +18,10 @@ vb b 0 dc 0
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.meas dc is_at FIND i(vs) AT=1
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.meas dc is_max max i(vs) from=0 to=3.5
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.meas dc vds_at when i(vs)=0.01
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* the following fails (probably does not recognize m or u):
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.meas dc vds_at2 when i(vs)=10000u
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.meas dc vds_at2 when i(vs)=10m
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.meas dc vd_diff1 trig i(vs) val=0.005 rise=1 targ i(vs) val=0.01 rise=1
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.meas dc vd_diff2 trig i(vs) val=0.005 rise=1 targ i(vs) val=0.01 rise=2
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*.meas ac fixed_diff trig AT = 10k targ v(out) val=0.1 rise=1
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*.meas ac vout_avg avg v(out) from=10k to=1MEG
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*.meas ac vout_integ integ v(out) from=20k to=500k
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*.meas ac freq_at2 when v(out)=0.1 fall=LAST
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*.meas ac bw_chk param='(vout_diff < 100k) ? 1 : 0'
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*.meas ac bw_chk2 param='(vout_diff > 500k) ? 1 : 0'
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*.meas ac vout_rms rms v(out) from=10 to=1G
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.control
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run
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*rusage all
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@ -0,0 +1,64 @@
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RC band pass example circuit
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* This netlist demonstrates the following:
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* global nodes (vdd, gnd)
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* .measure statements for delay and an example ternary operator
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* You can run the example circuit with this command:
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*
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* ngspice rc-meas-ac.sp
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* global nodes
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.global vdd gnd
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* autostop -- stop simulation early if .measure statements done
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*.option autostop
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vin in gnd dc 0 ac 1
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R1 in mid1 1k
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c1 mid1 gnd 1n
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C2 mid1 out 500p
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R2 out gnd 1k
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.control
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ac DEC 10 1k 10MEG
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meas ac vout_at FIND v(out) AT=1MEG
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meas ac vout_atr FIND vr(out) AT=1MEG
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meas ac vout_ati FIND vi(out) AT=1MEG
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meas ac vout_atm FIND vm(out) AT=1MEG
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meas ac vout_atp FIND vp(out) AT=1MEG
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meas ac vout_atd FIND vdb(out) AT=1MEG
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meas ac vout_max max v(out) from=1k to=10MEG
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meas ac freq_at when v(out)=0.1
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meas ac vout_diff trig v(out) val=0.1 rise=1 targ v(out) val=0.1 fall=1
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meas ac fixed_diff trig AT = 10k targ v(out) val=0.1 rise=1
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meas ac vout_avg avg v(out) from=10k to=1MEG
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meas ac vout_integ integ v(out) from=20k to=500k
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meas ac freq_at2 when v(out)=0.1 fall=LAST
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*meas ac bw_chk param='(vout_diff < 100k) ? 1 : 0'
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if (vout_diff < 100k)
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let bw_chk = 1
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else
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let bw_chk = 0
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end
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echo bw_chk = "$&bw_chk"
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*meas ac bw_chk2 param='(vout_diff > 500k) ? 1 : 0'
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if (vout_diff > 500k)
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let bw_chk2 = 1
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else
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let bw_chk2 = 0
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end
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echo bw_chk2 = "$&bw_chk2"
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meas ac vout_rms rms v(out) from=10 to=1G
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*rusage all
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plot v(out)
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plot ph(v(out))
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plot mag(v(out))
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plot db(v(out))
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.endc
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.end
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@ -516,7 +516,10 @@ static void measure_at(
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svalue = dScale->v_compdata[i].cx_real;
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}
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else if (cieq (meas->m_analysis,"sp")) {
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value = get_value(meas, d, i); //d->v_compdata[i].cx_real;
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if (d->v_compdata)
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value = get_value(meas, d, i); //d->v_compdata[i].cx_real;
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else
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value = d->v_realdata[i];
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svalue = dScale->v_realdata[i];
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}
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else {
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@ -589,7 +592,10 @@ static void measure_minMaxAvg(
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svalue = dScale->v_compdata[i].cx_real;
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}
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else if (cieq (meas->m_analysis,"sp")) {
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value = get_value(meas, d, i); //d->v_compdata[i].cx_real;
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if (d->v_compdata)
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value = get_value(meas, d, i); //d->v_compdata[i].cx_real;
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else
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value = d->v_realdata[i];
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svalue = dScale->v_realdata[i];
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}
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else {
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@ -1072,7 +1078,7 @@ static int measure_parse_when (
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wordlist *wl, /* in : word list to parse */
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char *errBuf /* in/out: buffer where we write error messages */
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) {
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int pCnt;
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int pCnt, err = 0;
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char *p, *pVar1, *pVar2;
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meas->m_vec = NULL;
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meas->m_vec2 = NULL;
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@ -1109,7 +1115,7 @@ static int measure_parse_when (
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correct_vec(meas);
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}
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else
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meas->m_val = atof(pVar2);
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meas->m_val = INPevaluate( &pVar2, &err, 1 );
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} else {
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if (measure_parse_stdParams(meas, wl, NULL, errBuf) == 0)
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return 0;
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|
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@ -1012,17 +1012,24 @@ inp_fix_ternary_operator_str( char *line )
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static void
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inp_fix_ternary_operator( struct line *start_card )
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{
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struct line *card;
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char *line;
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struct line *card;
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char *line;
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bool found_control = FALSE;
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for ( card = start_card; card != NULL; card = card->li_next ) {
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line = card->li_line;
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for ( card = start_card; card != NULL; card = card->li_next ) {
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line = card->li_line;
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if ( *line == '*' ) continue;
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if ( strstr( line, "?" ) && strstr( line, ":" ) ) {
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card->li_line = inp_fix_ternary_operator_str( line );
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}
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}
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/* exclude replacement of ternary function between .control and .endc */
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if ( ciprefix( ".control", line ) ) found_control = TRUE;
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if ( ciprefix( ".endc", line ) ) found_control = FALSE;
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if (found_control) continue;
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if ( *line == '*' ) continue;
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if ( strstr( line, "?" ) && strstr( line, ":" ) ) {
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card->li_line = inp_fix_ternary_operator_str( line );
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}
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}
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}
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/*-------------------------------------------------------------------------
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|
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@ -73,7 +73,7 @@ com_meas(wordlist *wl) {
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d = vec_get(vec_found);
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if (d) {
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/* get its value */
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sprintf(newval, "%f\0", d->v_realdata[0]);
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sprintf(newval, "%e\0", d->v_realdata[0]);
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tfree(vec_found);
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wl_index->wl_word = copy(newval);
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}
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@ -89,7 +89,7 @@ com_meas(wordlist *wl) {
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d = vec_get(vec_found);
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if (d) {
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*equal_ptr = '\0';
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sprintf(newval, "%s=%f\0", token, d->v_realdata[0]);
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sprintf(newval, "%s=%e\0", token, d->v_realdata[0]);
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// memory leak with first part of vec_found ?
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tfree(token);
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wl_index->wl_word = copy(newval);
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Loading…
Reference in New Issue