luke/ngspice
1
0
Fork 0
mirror of https://git.code.sf.net/p/ngspice/ngspice synced 2026-08-27 08:16:27 +02:00
Code Issues Packages Projects Releases Wiki Activity

bsimcmg, benchmark, TFIN FPITCH and L are instance parameters !

Browse Source
This commit is contained in:
rlar
2018-02-17 18:15:40 +01:00
parent a8ba4c9422
commit 6881264e80
9 changed files with 13 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files
bsimcmg_benchmark_test/ac.sp
+1
View File
@@ -16,6 +16,7 @@ vbs bulk 0 dc=0
* --- Transistor ---
m1 vout gate 0 bulk 0 nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
+ FPITCH = 4.00E-08
* --- Load ---
rl supply vout r=2k
bsimcmg_benchmark_test/gummel_n.sp
+1
View File
@@ -17,6 +17,7 @@ vbulk bulk 0 dc=0.0
* FIXME, parameter LSP has a different default !!
* see commit for bsimcmg_body.include
m1 drain gate source bulk 0 nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
+ FPITCH = 4.00E-08
* --- DC Analysis ---
.dc vdrain -0.1 0.1 0.001 vgate 0.0 1.0 0.2
bsimcmg_benchmark_test/gummel_p.sp
+1
View File
@@ -16,6 +16,7 @@ vbulk bulk 0 dc=0
* --- Transistor ---
m1 drain gate source bulk 0 pmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
+ FPITCH = 4.00E-08
* --- DC Analysis ---
.dc vdrain -0.1 0.1 0.001 vgate 0.0 -1.0 -0.2
bsimcmg_benchmark_test/invdc.sp
+3
View File
@@ -15,7 +15,10 @@ vin vi 0 dc=0.5
* --- Inverter Subcircuit ---
.subckt mg_inv vin vout vdd gnd
mp1 vout vin vdd gnd 0 pmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
+ FPITCH = 4.00E-08
mn1 vout vin gnd gnd 0 nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
+ FPITCH = 4.00E-08
.ends
* --- Inverter ---
bsimcmg_benchmark_test/inverter_transient.sp
+3
View File
@@ -15,7 +15,10 @@ vsig vi 0 dc=0.5 sin (0.5 0.5 1MEG)
* --- Inverter Subcircuit ---
.subckt mg_inv vin vout vdd gnd
mp1 vout vin vdd gnd 0 pmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1
+ FPITCH = 4.00E-08
mn1 vout vin gnd gnd 0 nmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1
+ FPITCH = 4.00E-08
.ends
* --- Inverter ---
bsimcmg_benchmark_test/modelcard.nmos
-3
View File
@@ -76,14 +76,12 @@
+ ETAMOB = 2
+ ETAQM = 0.54
+ EU = 1.2
+ FPITCH = 4.00E-08
+ HFIN = 3.00E-08
+ IGT = 2.5
+ K1RSCE = 0
+ KSATIV = 2
+ KT1 = 0
+ KT1L = 0
+ L = 2.50E-08
+ LINT = -2.00E-09
+ LPE0 = 0
+ LCDSCD = 5.00E-05
@@ -119,7 +117,6 @@
+ RTH0 = 0.225
+ TBGASUB = 0.000473
+ TBGBSUB = 636
+ TFIN = 1.40E-08
+ TGIDL = -0.007
+ TMEXP = 0
+ TNOM = 25
bsimcmg_benchmark_test/modelcard.pmos
-3
View File
@@ -76,14 +76,12 @@
+ ETAMOB = 4
+ ETAQM = 0.54
+ EU = 0.05
+ FPITCH = 4.00E-08
+ HFIN = 3.00E-08
+ IGT = 3.5
+ K1RSCE = 0
+ KSATIV = 1.592
+ KT1 = 0.08387
+ KT1L = 0
+ L = 2.50E-08
+ LINT = -2.5E-09
+ LPE0 = 0
+ LCDSCD = 0
@@ -119,7 +117,6 @@
+ RTH0 = 0.15
+ TBGASUB = 0.000473
+ TBGBSUB = 636
+ TFIN = 1.40E-08
+ TGIDL = -0.01
+ TMEXP = 0
+ TNOM = 25
bsimcmg_benchmark_test/noise.sp
+1
View File
@@ -17,6 +17,7 @@ lbias 1 drain 1m
cload drain 2 1m
rload 2 0 R=1 noise=0
X1 drain gate 0 bulk nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
+ FPITCH = 4.00E-08
* --- Analysis ---
.op
bsimcmg_benchmark_test/ringosc_17stg.sp
+3
View File
@@ -15,7 +15,10 @@ vdd supply 0 dc=1.0
* --- Inverter Subcircuit ---
.subckt mg_inv vin vout vdd gnd
mp1 vout vin vdd gnd 0 pmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1
+ FPITCH = 4.00E-08
mn1 vout vin gnd gnd 0 nmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1
+ FPITCH = 4.00E-08
.ends
* --- 17 Stage Ring oscillator ---