bsim6.va, disable __THERMAL_NODE__ and __SHMOD__

modify Benchmark accordingly,
there is no more "thermal" node

Benchmark_test/gummel_nmos.sp

@@ -1,8 +1,8 @@
 *Sample netlist for BSIM6.0
 *Drain current symmetry for nmos
+* (exec-spice "ngspice %s" t)
 .option abstol=1e-6 reltol=1e-6 post ingold
 
-.hdl "bsim6.va"
 .include "modelcard.nmos"
 
 * --- Voltage Sources ---
@@ -13,7 +13,7 @@ vbulk bulk 0 dc=0.0
 
 
 * --- Transistor ---
-X1 drain gate source bulk bsim6 W=10u L=10u 
+M1 drain gate source bulk  mn W=10u L=10u 
 
 * --- DC Analysis ---
 .dc vdrain -0.1 0.1 0.001 vgate 0.0 1.0 0.2
@@ -24,4 +24,8 @@ X1 drain gate source bulk bsim6 W=10u L=10u
 .probe dc gx4=deriv(gx3)
 .print dc par'ids' par'gx' par'gx2' par'gx3' par 'gx4'
 
+.control
+run
+plot -i(vdrain)
+.endc
 .end

Benchmark_test/gummel_pmos.sp

@@ -1,8 +1,8 @@
 *Sample netlist for BSIM6.0
 *Drain current symmetry
+* (exec-spice "ngspice %s" t)
 .option abstol=1e-6 reltol=1e-6 post ingold
 
-.hdl "bsim6.va"
 .include "modelcard.pmos"
 
 * --- Voltage Sources ---
@@ -13,10 +13,10 @@ vbulk bulk 0 dc=0
 
 
 * --- Transistor ---
-X1 drain gate source bulk pmos W=10e-6 L=10e-6
+M1 drain gate source bulk  mp W=10e-6 L=10e-6
 
 * --- DC Analysis ---
-.dc vdrain -0.1 0.1 0.001 vgate -1 -0.4 -0.3
+.dc vdrain -0.1 0.1 0.001 vgate -1 -0.4 0.3
 .probe dc ids=par'-i(vdrain)'
 .probe dc gx=deriv(ids)
 .probe dc gx2=deriv(gx)
@@ -24,4 +24,8 @@ X1 drain gate source bulk pmos W=10e-6 L=10e-6
 .probe dc gx4=deriv(gx3)
 .print dc par'ids' par'gx' par'gx2' par'gx3' par 'gx4'
 
+.control
+run
+plot -i(vdrain)
+.endc
 .end

Benchmark_test/idvd_nmos.sp

@@ -11,10 +11,9 @@ vd d  0 dc=1.3
 vg g  0 dc=0
 vs s  0 dc=0
 vb b  0 dc=0
-vt t  0 dc=0
 
 * --- Transistor ---
-M1 d g s b t mn W=10e-6 L=10e-6
+M1 d g s b  mn W=10e-6 L=10e-6
 
 * --- DC Analysis ---
 .dc  vd 0.0 1.3 0.01 vg 0.4 1 0.3

Benchmark_test/idvd_pmos.sp

@@ -12,10 +12,9 @@ vd d  0 dc=-1
 vg g  0 dc=0
 vs s  0 dc=0
 vb b  0 dc=0
-vt t  0 dc=0
 
 * --- Transistor ---
-M1 d g s b t  mp W=10e-6 L=10e-6
+M1 d g s b  mp W=10e-6 L=10e-6
 
 * --- DC Analysis ---
 .dc  vd -1.3 0.0 0.01 vg -1 -0.4 0.3

Benchmark_test/idvg_nmos.sp

@@ -9,10 +9,9 @@ vd d  0 dc=50m
 vg g  0 dc=0.0
 vs s  0 dc=0.0
 vb b  0 dc=0.0
-vt t  0 dc=0
 
 * --- Transistor ---
-M1 d g s b t  mn W = 10e-6 L = 10e-6
+M1 d g s b   mn W = 10e-6 L = 10e-6
 
 * --- DC Analysis ---
 .dc vg -1.3 1.3 0.01 vb -0.3 0 0.1

Benchmark_test/idvg_pmos.sp

@@ -10,10 +10,9 @@ vd d  0 dc=-0.05
 vg g  0 dc=0.0
 vs s  0 dc=0.0
 vb b  0 dc=0.0
-vt t  0 dc=0
 
 * --- Transistor ---
-M1 d g s b t  mp W=10e-6 L=10e-6
+M1 d g s b  mp W=10e-6 L=10e-6
 
 * --- DC Analysis ---
 .dc  vg -1.3.0 1.3 0.01 vb 0 -0.3 -0.1

Benchmark_test/inv_dc.sp

@@ -11,8 +11,8 @@ vin   vi 0 dc=0.5
 
 * --- Inverter Subcircuit ---
 .subckt inverter vin vout vdd gnd
-    mXp1 vout vin vdd gnd 0  mp W=10u L=10u
+    mXp1 vout vin vdd gnd  mp W=10u L=10u
-    mXn1 vout vin gnd gnd 0  mn W=10u L=10u
+    mXn1 vout vin gnd gnd  mn W=10u L=10u
 .ends
 
 * --- Inverter ---

Benchmark_test/inverter_transient.sp

@@ -12,8 +12,8 @@ vin  vi  0 dc=0.5 sin (0.5 0.5 1MEG)
 
 * --- Inverter Subcircuit ---
 .subckt inverter vin vout vdd gnd
-    Mp1 vout vin vdd gnd 0  mp W=10u L=10u
+    Mp1 vout vin vdd gnd  mp W=10u L=10u
-    Mn1 vout vin gnd gnd 0  mn W=10u L=10u
+    Mn1 vout vin gnd gnd  mn W=10u L=10u
 .ends
 
 * --- Inverter ---

Benchmark_test/ringosc_17.sp

@@ -12,8 +12,8 @@ vdd supply  0 dc=1.0
 
 * --- Inverter Subcircuit ---
 .subckt inverter vin vout vdd gnd
-    Mp1 vout vin vdd gnd 0  mp  W=10e-6 L=10e-6
+    Mp1 vout vin vdd gnd  mp  W=10e-6 L=10e-6
-    Mn1 vout vin gnd gnd 0  mn  W=10e-6 L=10e-6
+    Mn1 vout vin gnd gnd  mn  W=10e-6 L=10e-6
 .ends
 
 * --- 17 Stage Ring oscillator ---

src/spicelib/devices/adms/bsim6/admsva/bsim6.va

@@ -64,7 +64,7 @@
 `define __TNOISW__
 `define __RGATEMOD__
 `define __RBODYMOD__
-`define __SHMOD__
+//`define __SHMOD__
 
 
 // Normalized pinch-off voltage including PD
@@ -568,7 +568,7 @@
 `define IPIoz(nam,def,uni,        des) (*units=uni, type="instance",  desc=des*) parameter integer nam=def from(  0:inf);
 
 
-`define __THERMAL_NODE__
+//`define __THERMAL_NODE__
 `ifdef __THERMAL_NODE__
 
 	module bsim6(d, g, s, b, t);