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Further fix for PWL bugs introduced by 9c71db3 (Fix for Bug #607) and 

partially fixed by 79c69e0 and 9c75367.  This also fixes Bug #468 -
"Bugs in src/spicelib/devices/vsrc/vsrcacct.c for PWL source."
This commit is contained in:
Giles Atkinson 2023-06-20 09:50:06 +01:00 committed by Holger Vogt
parent 5114d6c2f4
commit 5f6a6a27d8
2 changed files with 5 additions and 0 deletions
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4
src/spicelib/devices/vsrc/vsrcacct.c
View File

@ -172,7 +172,11 @@ VSRCaccept(CKTcircuit *ckt, GENmodel *inModel)
period = end -
here->VSRCcoeffs[here->VSRCrBreakpt];
time -=
here->VSRCcoeffs[here->VSRCrBreakpt];
time -= period * floor(time / period);
time +=
here->VSRCcoeffs[here->VSRCrBreakpt];
} else {
here->VSRCbreak_time = ckt->CKTfinalTime;
break;

1
src/spicelib/devices/vsrc/vsrcload.c
View File

@ -318,6 +318,7 @@ VSRCload(GENmodel *inModel, CKTcircuit *ckt)
period = end_time -
here->VSRCcoeffs[here->VSRCrBreakpt];
time -= here->VSRCcoeffs[here->VSRCrBreakpt];
time -= period * floor(time / period);
time += here->VSRCcoeffs[here->VSRCrBreakpt];
} else {