luke
/
ngspice
mirror of https://git.code.sf.net/p/ngspice/ngspice
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Changed line-ending from DOS to UNIX

This commit is contained in:
rlar 2012-10-20 19:48:48 +02:00
parent 0853c374a1
commit 5d1bc8e55d
2 changed files with 53 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

66
src/xspice/examples/rca3040.in
View File

@ -1,33 +1,33 @@
rca3040 ckt - rca 3040 wideband amplifier
.ac dec 10 1 10ghz
.dc vin -0.25 0.25 0.005
.tran 2.0ns 200ns
vin 1 0 sin(0 0.1 50meg 0.5ns) ac 1
vcc 2 0 15.0
vee 3 0 -15.0
rs1 30 1 1k
rs2 31 0 1k
r1 5 3 4.8k
r2 6 3 4.8k
r3 9 3 811
r4 8 3 2.17k
r5 8 0 820
r6 2 14 1.32k
r7 2 12 4.5k
r8 2 15 1.32k
r9 16 0 5.25k
r10 17 0 5.25k
q1 2 30 5 qnl
q2 2 31 6 qnl
q3 10 5 7 qnl
q4 11 6 7 qnl
q5 14 12 10 qnl
q6 15 12 11 qnl
q7 12 12 13 qnl
q8 13 13 0 qnl
q9 7 8 9 qnl
q10 2 15 16 qnl
q11 2 14 17 qnl
.model qnl npn bf=80 rb=100 ccs=2pf tf=0.3ns tr=6ns cje=3pf
+ cjc=2pf va 50
.end
rca3040 ckt - rca 3040 wideband amplifier
.ac dec 10 1 10ghz
.dc vin -0.25 0.25 0.005
.tran 2.0ns 200ns
vin 1 0 sin(0 0.1 50meg 0.5ns) ac 1
vcc 2 0 15.0
vee 3 0 -15.0
rs1 30 1 1k
rs2 31 0 1k
r1 5 3 4.8k
r2 6 3 4.8k
r3 9 3 811
r4 8 3 2.17k
r5 8 0 820
r6 2 14 1.32k
r7 2 12 4.5k
r8 2 15 1.32k
r9 16 0 5.25k
r10 17 0 5.25k
q1 2 30 5 qnl
q2 2 31 6 qnl
q3 10 5 7 qnl
q4 11 6 7 qnl
q5 14 12 10 qnl
q6 15 12 11 qnl
q7 12 12 13 qnl
q8 13 13 0 qnl
q9 7 8 9 qnl
q10 2 15 16 qnl
q11 2 14 17 qnl
.model qnl npn bf=80 rb=100 ccs=2pf tf=0.3ns tr=6ns cje=3pf
+ cjc=2pf va 50
.end

40
src/xspice/examples/rtlinv.in
View File

@ -1,20 +1,20 @@
rtlinv ckt - cascaded rtl inverters
.width in=72
.opt acct list node lvlcod=2
.dc vin 0.0 2.5 0.025
.tran 2ns 200ns
vcc 6 0 5
vin 1 0 pulse(0 5 2ns 2ns 2ns 80ns)
rb1 1 2 10k
rc1 6 3 1k
q1 3 2 0 qnd
rb2 3 4 10k
q2 5 4 0 qnd
rc2 6 5 1k
.model qnd npn(bf=50 rb=70 rc=40 ccs=2pf tf=0.1ns tr=10ns cje=0.9pf
+ cjc=1.5pf pc=0.85 va=50)
.print dc v(3) v(5)
.plot dc v(3)
.print tran v(3) v(5)
.plot tran v(3) v(5) v(1)
.end
rtlinv ckt - cascaded rtl inverters
.width in=72
.opt acct list node lvlcod=2
.dc vin 0.0 2.5 0.025
.tran 2ns 200ns
vcc 6 0 5
vin 1 0 pulse(0 5 2ns 2ns 2ns 80ns)
rb1 1 2 10k
rc1 6 3 1k
q1 3 2 0 qnd
rb2 3 4 10k
q2 5 4 0 qnd
rc2 6 5 1k
.model qnd npn(bf=50 rb=70 rc=40 ccs=2pf tf=0.1ns tr=10ns cje=0.9pf
+ cjc=1.5pf pc=0.85 va=50)
.print dc v(3) v(5)
.plot dc v(3)
.print tran v(3) v(5)
.plot tran v(3) v(5) v(1)
.end