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Merge branch 'pre-master-46' of ssh://git.code.sf.net/p/ngspice/ngspice into pre-master-46

This commit is contained in:
dwarning 2026-03-03 18:33:16 +01:00
parent ad44b4ff4c 5855c442e1
commit 5458f15d6b
2 changed files with 6 additions and 6 deletions
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6
src/spicelib/devices/isrc/isrcload.c
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@ -205,18 +205,18 @@ ISRCload(GENmodel *inModel, CKTcircuit *ckt)
case SFFM: {
double VO, VA, FM, MDI, FC, TD, PHASEM, PHASEC;
double VO, VA, FC, MDI, FM, TD, PHASEM, PHASEC;
double phasec;
double phasem;
static bool warn1 = FALSE, warn2 = FALSE;
VO = here->ISRCcoeffs[0];
VA = here->ISRCcoeffs[1];
FM = here->ISRCfunctionOrder > 2
FC = here->ISRCfunctionOrder > 2
? here->ISRCcoeffs[2] : (5./ckt->CKTfinalTime);
MDI = here->ISRCfunctionOrder > 3
? here->ISRCcoeffs[3] : 90.0;
FC = here->ISRCfunctionOrder > 4
FM = here->ISRCfunctionOrder > 4
&& here->ISRCcoeffs[4]
? here->ISRCcoeffs[4] : (500./ckt->CKTfinalTime);
TD = here->ISRCfunctionOrder > 5

6
src/spicelib/devices/vsrc/vsrcload.c
View File

@ -233,18 +233,18 @@ VSRCload(GENmodel *inModel, CKTcircuit *ckt)
case SFFM: {
double VO, VA, FM, MDI, FC, TD, PHASEM, PHASEC;
double VO, VA, FC, MDI, FM, TD, PHASEM, PHASEC;
double phasec;
double phasem;
static bool warn1 = FALSE, warn2 = FALSE;
VO = here->VSRCcoeffs[0];
VA = here->VSRCcoeffs[1];
FM = here->VSRCfunctionOrder > 2
FC = here->VSRCfunctionOrder > 2
? here->VSRCcoeffs[2] : (5./ckt->CKTfinalTime);
MDI = here->VSRCfunctionOrder > 3
? here->VSRCcoeffs[3] : 90.0; /* 0.9 * FC / FM */
FC = here->VSRCfunctionOrder > 4
FM = here->VSRCfunctionOrder > 4
&& here->VSRCcoeffs[4] /* test if not 0 */
? here->VSRCcoeffs[4] : (500./ckt->CKTfinalTime);
TD = here->VSRCfunctionOrder > 5