Updated some bsim3 tests to run with the BSIM3 model instead of the BSIMv32 model

This commit is contained in:
Francesco Lannutti 2013-04-20 00:25:12 +02:00
parent a707256456
commit 4ffa4c73c4
4 changed files with 6 additions and 26 deletions

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@ -2,7 +2,7 @@
*Berkeley Spice Compatibility
* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20
.model N1 NMOS
+Level= 8 version=3.2.2
+Level= 8 version=3.3.0
+Tnom=27.0
+Nch= 2.498E+17 Tox=9E-09 Xj=1.00000E-07
+Lint=9.36e-8 Wint=1.47e-7
@ -33,9 +33,3 @@
+Ute=-1.48
+Ua1= 3.31E-10 Ub1= 2.61E-19 Uc1= -3.42e-10
+Kt1l=0 Prt=764.3

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@ -1,5 +1,5 @@
.model P1 PMOS
+Level= 8 version=3.2.2
+Level= 8 version=3.3.0
+Tnom=27.0
+Nch= 3.533024E+17 Tox=9E-09 Xj=1.00000E-07
+Lint=6.23e-8 Wint=1.22e-7
@ -25,7 +25,3 @@
+Ute= -1.5
+Ua1= 4.312e-9 Ub1= 6.65e-19 Uc1= 0
+Kt1l=0

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@ -28,8 +28,8 @@ Vdd Vdd 0 5
Va A 0 pulse 0 5 10ns .1ns .1ns 15ns 30ns
Vb B 0 0
.model nmos nmos level=8 version=3.2.2
.model pmos pmos level=8 version=3.2.2
.model nmos nmos level=8 version=3.3.0
.model pmos pmos level=8 version=3.3.0
* transient analysis
.tran 1ns 60ns
@ -37,4 +37,3 @@ Vb B 0 0
.print tran a b v(9) v(8)
.END

View File

@ -34,20 +34,11 @@ M13 3 Lnot 0 0 NMOS w=1.8u l=1.2u
Vcc vdd 0 5
vin in 0 pulse 0 5 1ns .1ns .1ns .8ns 5ns
.model nmos nmos level=8 version=3.2.2
.model pmos pmos level=8 version=3.2.2
.model nmos nmos level=8 version=3.3.0
.model pmos pmos level=8 version=3.3.0
.tran 1ns 10ns
.print tran in out
.options noacct
.END