Fix the voltage pulse statements.
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@ -14,7 +14,7 @@ U4 JKFF(1) $G_DPWR $G_DGND HIGH CLEAR QC HIGH HIGH QD 11
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*** input sources ***
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vclk 100 0 pulse( 0.0 1.0 50ns 0ns 0ns 50ns 100ns )
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vreset 200 0 pulse( 1.0 0.0 10ns 0ns 0ns 50ns )
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vreset 200 0 pulse( 1.0 0.0 10ns 0ns 0ns 50ns 100ns 1 )
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vhigh 300 0 DC 1.0
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*** adc_bridge blocks ***
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@ -13,7 +13,7 @@ Mixed IO types with conversion of Pspice nand and divider.
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.tran 1e-5 1e-3
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.save all
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*
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v1 1 0 0.0 pulse(0 1 1e-4 1e-6)
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v1 1 0 0.0 pulse(0 1 1e-4 1e-6 1e-6 1e-4 2e-4)
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r1 1 0 1k
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*
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abridge1 [1] [enable] atod
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