Fix the voltage pulse statements.

This commit is contained in:
Brian Taylor 2026-03-23 19:43:12 -07:00
parent a044a43dd4
commit 3657b9f8ce
2 changed files with 2 additions and 2 deletions

View File

@ -14,7 +14,7 @@ U4 JKFF(1) $G_DPWR $G_DGND HIGH CLEAR QC HIGH HIGH QD 11
*** input sources ***
vclk 100 0 pulse( 0.0 1.0 50ns 0ns 0ns 50ns 100ns )
vreset 200 0 pulse( 1.0 0.0 10ns 0ns 0ns 50ns )
vreset 200 0 pulse( 1.0 0.0 10ns 0ns 0ns 50ns 100ns 1 )
vhigh 300 0 DC 1.0
*** adc_bridge blocks ***

View File

@ -13,7 +13,7 @@ Mixed IO types with conversion of Pspice nand and divider.
.tran 1e-5 1e-3
.save all
*
v1 1 0 0.0 pulse(0 1 1e-4 1e-6)
v1 1 0 0.0 pulse(0 1 1e-4 1e-6 1e-6 1e-4 2e-4)
r1 1 0 1k
*
abridge1 [1] [enable] atod