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Examples for single event effects (SEE): Inverters and SRAM cell

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Holger Vogt 2025-05-20 17:19:12 +02:00
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45
examples/xspice/see/ihp_inverter_set.net Normal file
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* IHP Open PDK
* simple inverter
* Path to the PDK
*.include "D:\Spice_general\skywater-pdk\libraries\sky130_fd_pr\latest\models\corners/tt.spice"
.lib "D:\Spice_general\IHP-Open-PDK\ihp-sg13g2\libs.tech\ngspice\models\cornerMOSlv.lib" mos_tt
*.include lib_out1.lib
.param vdd = 1.2
.param deltat=11n
* the voltage sources:
Vdd vd gnd DC 'vdd'
V1 in gnd pulse(0 'vdd' 0p 200p 100p 5n 10n)
* Eponential current source
Iset out 0 EXP(0 2.5m 'deltat' 10p 'deltat' 500p)
*Cset out 0 10f
Xnot1 in vdd vss out not1
Vmeasvss vss 0 0
Vmeasvdd vd vdd 0
.subckt not1 a vdd vss z
xm01 z a vdd vdd sg13_lv_pmos l=0.15u w=0.99u as=0.26235p ad=0.26235p ps=2.51u pd=2.51u
xm02 z a vss vss sg13_lv_nmos l=0.15u w=0.495u as=0.131175p ad=0.131175p ps=1.52u pd=1.52u
c3 a vss 0.384f
c2 z vss 0.576f
.ends
* simulation command:
.tran 100ps 50ns ; 0 10p
.options method=gear
.control
run
rusage
*set nolegend
set xbrushwidth=3
plot i(Vmeasvss) i(Vmeasvdd)
plot in out
.endc
.end

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examples/xspice/see/ihp_simple_sram_seegen.net Normal file
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* IHP Open PDK
* simple SRAM cell, exponential current pulses
* Path to the PDK
*.include "D:\Spice_general\skywater-pdk\libraries\sky130_fd_pr\latest\models\corners/tt.spice"
.lib "D:\Spice_general\IHP-Open-PDK\ihp-sg13g2\libs.tech\ngspice\models\cornerMOSlv.lib" mos_tt
*.include lib_out1.lib
.param vdd = 1.2
.param deltat=11n deltat2=27n
.param tochar = 1e-13
.param talpha = 500p tbeta=10p
.param Inull = 'tochar/(talpha-tbeta)'
* the voltage sources:
Vdd vd gnd DC 'vdd'
Vwl wl 0 0 PULSE 0 'vdd' 45n 1n 1n 7n 1
Vbl bl 0 'vdd'
Vbln bln 0 0
*V1 in gnd pulse(0 'vdd' 0p 200p 100p 5n 10n)
* Eponential current source without control input
aseegen1 NULL [%id(n1 m1) %id(n2 m2) %id(n1 m1) %id(n2 m2)] seemod1
.model seemod1 seegen (tdelay = 11n tperiod=25n inull='Inull')
Xnot1 n1 vdd vss n2 not1
Xnot2 n2 vdd vss n1 not1
xmo02 n2 wl bl vss sg13_lv_nmos l=0.15u w=0.495u as=0.131175p ad=0.131175p ps=1.52u pd=1.52u
xmo01 n1 wl bln vss sg13_lv_nmos l=0.15u w=0.495u as=0.131175p ad=0.131175p ps=1.52u pd=1.52u
Vmeasvss vss 0 0
Vmeasvdd vd vdd 0
Vm1 m1 0 0
Vm2 m2 0 0
.subckt not1 a vdd vss z
xm01 z a vdd vdd sg13_lv_pmos l=0.15u w=0.99u as=0.26235p ad=0.26235p ps=2.51u pd=2.51u
xm02 z a vss vss sg13_lv_nmos l=0.15u w=0.495u as=0.131175p ad=0.131175p ps=1.52u pd=1.52u
c3 a vss 0.384f
c2 z vss 0.576f
.ends
* starting condition for SRAM cell
.ic v(n2)=0 v(n1)='vdd'
* simulation command:
.tran 100ps 100ns ; 0 10p
.options method=gear
.control
run
rusage
*set nolegend
set xbrushwidth=3
plot i(Vmeasvss) i(Vmeasvdd)
plot n1 n2+2 wl+4 i(vm1)*10000+6 i(vm2)*10000+8
.endc
.end

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examples/xspice/see/ihp_simple_sram_seegen_ctrl.net Normal file
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* IHP Open PDK
* simple SRAM cell, exponential current pulses
* Path to the PDK
*.include "D:\Spice_general\skywater-pdk\libraries\sky130_fd_pr\latest\models\corners/tt.spice"
.lib "D:\Spice_general\IHP-Open-PDK\ihp-sg13g2\libs.tech\ngspice\models\cornerMOSlv.lib" mos_tt
*.include lib_out1.lib
.param vdd = 1.2
.param deltat=11n deltat2=27n
.param tochar = 1e-13
.param talpha = 500p tbeta=10p
.param Inull = 'tochar/(talpha-tbeta)'
* the voltage sources:
Vdd vd gnd DC 'vdd'
Vwl wl 0 0 PULSE 0 'vdd' 45n 1n 1n 7n 1
Vbl bl 0 'vdd'
Vbln bln 0 0
Vctrl ctrl 0 pulse (0 1 10n 1n 1n 1 1)
*V1 in gnd pulse(0 'vdd' 0p 200p 100p 5n 10n)
* Eponential current source with control input
aseegen1 ctrl [%id(n1 m1) %id(n2 m2) %id(n1 m1) %id(n2 m2)] seemod1
.model seemod1 seegen (tdelay = 8n tperiod=25n)
Xnot1 n1 vdd vss n2 not1
Xnot2 n2 vdd vss n1 not1
xmo02 n2 wl bl vss sg13_lv_nmos l=0.15u w=0.495u as=0.131175p ad=0.131175p ps=1.52u pd=1.52u
xmo01 n1 wl bln vss sg13_lv_nmos l=0.15u w=0.495u as=0.131175p ad=0.131175p ps=1.52u pd=1.52u
Vmeasvss vss 0 0
Vmeasvdd vd vdd 0
Vm1 m1 0 0
Vm2 m2 0 0
.subckt not1 a vdd vss z
xm01 z a vdd vdd sg13_lv_pmos l=0.15u w=0.99u as=0.26235p ad=0.26235p ps=2.51u pd=2.51u
xm02 z a vss vss sg13_lv_nmos l=0.15u w=0.495u as=0.131175p ad=0.131175p ps=1.52u pd=1.52u
c3 a vss 0.384f
c2 z vss 0.576f
.ends
* starting condition for SRAM cell
.ic v(n2)=0 v(n1)='vdd'
* simulation command:
.tran 100ps 100ns ; 0 10p
.options method=gear
.control
run
rusage
*set nolegend
set xbrushwidth=3
plot i(Vmeasvss) i(Vmeasvdd)
plot n1 n2+2 wl+4 i(vm1)*10000+6 i(vm2)*10000+8
.endc
.end

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examples/xspice/see/ihp_simple_sram_set.net Normal file
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* IHP Open PDK
* simple SRAM cell, exponential current pulses
* Path to the PDK
*.include "D:\Spice_general\skywater-pdk\libraries\sky130_fd_pr\latest\models\corners/tt.spice"
.lib "D:\Spice_general\IHP-Open-PDK\ihp-sg13g2\libs.tech\ngspice\models\cornerMOSlv.lib" mos_tt
*.include lib_out1.lib
.param vdd = 1.2
.param deltat=11n deltat2=27n
.param tochar = 1e-13
.param talpha = 500p tbeta=10p
.param Inull = 'tochar/(talpha-tbeta)'
* the voltage sources:
Vdd vd gnd DC 'vdd'
Vwl wl 0 0 PULSE 0 'vdd' 45n 1n 1n 7n 1
Vbl bl 0 'vdd'
Vbln bln 0 0
*V1 in gnd pulse(0 'vdd' 0p 200p 100p 5n 10n)
* Eponential current source
Iset1 n1 m1 EXP(0 'Inull' 'deltat' 'tbeta' 'deltat' 'talpha')
Iset2 n2 m2 EXP(0 'Inull' 'deltat2' 'tbeta' 'deltat2' 'talpha')
Iset3 n1 m1 EXP(0 'Inull' 'deltat+50n' 'tbeta' 'deltat+50n' 'talpha')
Iset4 n2 m2 EXP(0 'Inull' 'deltat2+50n' 'tbeta' 'deltat2+50n' 'talpha')
*Cset out 0 10f
Xnot1 n1 vdd vss n2 not1
Xnot2 n2 vdd vss n1 not1
xmo02 n2 wl bl vss sg13_lv_nmos l=0.15u w=0.495u as=0.131175p ad=0.131175p ps=1.52u pd=1.52u
xmo01 n1 wl bln vss sg13_lv_nmos l=0.15u w=0.495u as=0.131175p ad=0.131175p ps=1.52u pd=1.52u
Vmeasvss vss 0 0
Vmeasvdd vd vdd 0
Vm1 m1 0 0
Vm2 m2 0 0
.subckt not1 a vdd vss z
xm01 z a vdd vdd sg13_lv_pmos l=0.15u w=0.99u as=0.26235p ad=0.26235p ps=2.51u pd=2.51u
xm02 z a vss vss sg13_lv_nmos l=0.15u w=0.495u as=0.131175p ad=0.131175p ps=1.52u pd=1.52u
c3 a vss 0.384f
c2 z vss 0.576f
.ends
* starting condition for SRAM cell
.ic v(n2)=0 v(n1)='vdd'
* simulation command:
.tran 100ps 100ns ; 0 10p
.options method=gear
.control
run
rusage
*set nolegend
set xbrushwidth=3
plot i(Vmeasvss) i(Vmeasvdd)
plot n1 n2+2 wl+4 i(vm1)*10000+6 i(vm2)*10000+8
.endc
.end

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examples/xspice/see/ihp_two_inverters_set.net Normal file
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* IHP Open PDK
* simple inverter
* Path to the PDK
*.include "D:\Spice_general\skywater-pdk\libraries\sky130_fd_pr\latest\models\corners/tt.spice"
.lib "D:\Spice_general\IHP-Open-PDK\ihp-sg13g2\libs.tech\ngspice\models\cornerMOSlv.lib" mos_tt
*.include lib_out1.lib
.param vdd = 1.2
.param deltat=11n deltat2=27n
* the voltage sources:
Vdd vd gnd DC 'vdd'
V1 in gnd pulse(0 'vdd' 0p 200p 100p 5n 10n)
* Eponential current source
Iset1 out1 0 EXP(0 250u 'deltat' 10p 'deltat' 500p)
Iset2 out1 0 EXP(0 250u 'deltat2' 10p 'deltat2' 500p)
*Cset out 0 10f
Xnot1 in vdd vss out1 not1
Xnot2 out1 vdd vss out not1
Vmeasvss vss 0 0
Vmeasvdd vd vdd 0
.subckt not1 a vdd vss z
xm01 z a vdd vdd sg13_lv_pmos l=0.15u w=0.99u as=0.26235p ad=0.26235p ps=2.51u pd=2.51u
xm02 z a vss vss sg13_lv_nmos l=0.15u w=0.495u as=0.131175p ad=0.131175p ps=1.52u pd=1.52u
c3 a vss 0.384f
c2 z vss 0.576f
.ends
* simulation command:
.tran 100ps 50ns ; 0 10p
.options method=gear
.control
run
rusage
*set nolegend
set xbrushwidth=3
plot i(Vmeasvss) i(Vmeasvdd)
plot in out1+2 out+4
.endc
.end

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examples/xspice/see/seegen_cm1.cir Normal file
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Test of seegen code model
aseegen1 NULL [%id(n1 p1) %id(n2 p2) %id(n3 p3)] seemod1
.model seemod1 seegen (tdelay = 5n tperiod=4.5n)
Rsee1 n1 0 1
Vmeas1 p1 0 0
Rsee2 n2 0 1
Vmeas2 p2 0 0
Rsee3 n3 0 1
Vmeas3 p3 0 0
.control
tran 10p 35n
set xbrushwidth=3
plot i(Vmeas1) i(Vmeas2)+200u i(Vmeas3)+400u
.endc
.end

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examples/xspice/see/set1.cir Normal file
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SET pulse test
.param alpha = 10p beta = 500p deltat = 1n
* Arbitrary currnt source with expression
Bset1 1 0 I = ternary_fcn(TIME < 'deltat', 0, 2.5m * (exp(-(TIME-'deltat')/'alpha')-exp(-(TIME-'deltat')/'beta')))
R1 1 11 1
Vmeas 11 0 0
* Eponential current source
Iset 2 0 EXP(0 -2.5m 'deltat' 10p 'deltat' 500p)
R2 2 22 1
Vmeas2 22 0 0
.control
tran 1p 10n
plot I(Vmeas)-I(Vmeas2)
plot I(Vmeas) I(Vmeas2)
.endc
.end