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update to existing examples (for improved readability)

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h_vogt 2017-07-06 12:12:10 +02:00
parent d48ea30348
commit 2c705fbbdc
2 changed files with 163 additions and 160 deletions
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81
examples/xspice/pll/pll-xspice-fstep.cir
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* pll circuit using xspice code models *** pll circuit using xspice code models
* three frequencies generate steps in control voltage v(cont) *** three reference frequencies generate steps in control voltage v(cont)
*** titel, ** sub-title, * select
.param vcc=3.3 .param vcc=3.3
.param divisor=40 .param divisor=40
@ -10,91 +12,92 @@
.csparam f2='fref2' .csparam f2='fref2'
.csparam f3='fref3' .csparam f3='fref3'
* digital zero and one ** digital zero and one
.global d_d0 d_d1 .global d_d0 d_d1
vdd dd 0 dc 'vcc' vdd dd 0 dc 'vcc'
* 10 MHz reference frequency ** 10 MHz reference frequency
* PULSE(V1 V2 TD TR TF PW PER) ** PULSE(V1 V2 TD TR TF PW PER)
vref ref 0 dc 0 pulse(0 'vcc' 10n 1n 1n '1/fref/2' '1/fref') vref ref 0 dc 0 pulse(0 'vcc' 10n 1n 1n '1/fref/2' '1/fref')
abridgeref [ref] [d_ref] adc_vbuf abridgeref [ref] [d_ref] adc_vbuf
.model adc_vbuf adc_bridge(in_low = 0.5 in_high = 0.5) .model adc_vbuf adc_bridge(in_low = 0.5 in_high = 0.5)
*digital zero ** digital zero
vzero z 0 dc 0 vzero z 0 dc 0
abridgev3 [z] [d_d0] adc_vbuf abridgev3 [z] [d_d0] adc_vbuf
.model adc_vbuf adc_bridge(in_low = 'vcc*0.5' in_high = 'vcc*0.5') .model adc_vbuf adc_bridge(in_low = 'vcc*0.5' in_high = 'vcc*0.5')
*digital one ** digital one
ainv1 d_d0 d_d1 invd1 ainv1 d_d0 d_d1 invd1
.model invd1 d_inverter(rise_delay = 1e-10 fall_delay = 1e-10) .model invd1 d_inverter(rise_delay = 1e-10 fall_delay = 1e-10)
* vco ** vco
* buf: analog out ** buf: analog out
* d_digout: digital out ** d_digout: digital out
* cont: analog control voltage ** vcont: analog control voltage
* dd: analog supply voltage ** dd: analog supply voltage
*.include vco_sub.cir *.include vco_sub.cir
*xvco buf d_digout cont dd ro_vco *xvco buf d_digout vcont dd ro_vco
.include vco_sub_new.cir .include vco_sub_new.cir
xvco buf d_digout cont dd d_osc_vco xvco buf d_digout vcont dd d_osc_vco
* digital divider ** digital divider
adiv1 d_digout d_divout divider adiv1 d_digout d_divout divider
.model divider d_fdiv(div_factor = 'divisor' high_cycles = 'divisor/2' .model divider d_fdiv(div_factor = 'divisor' high_cycles = 'divisor/2'
+ i_count = 4 rise_delay = 1e-10 + i_count = 4 rise_delay = 1e-10
+ fall_delay = 1e-10) + fall_delay = 1e-10)
* frequency phase detector ** frequency phase detector
.include f-p-det-d-sub.cir .include f-p-det-d-sub.cir
Xfpdet d_divout d_ref d_U d_Un d_D d_Dn f-p-det Xfpdet d_divout d_ref d_U d_Un d_D d_Dn f-p-det
* loop filter ** loop filter
*2nd or 3rd order, transistors as switches ** 2nd or 3rd order, transistors as switches
.include loop-filter-2.cir .include loop-filter-2.cir
Xlf d_Un d_D cont loopf Xlf d_Un d_D vcont loopf
* 2nd order, Exxxx voltage controlled current sources as 'switches' ** 2nd order, Exxxx voltage controlled current sources as 'switches'
* loop filter current sources as charge pump ** loop filter current sources as charge pump
*.include loop-filter.cir *.include loop-filter.cir
*Xlf d_U d_D cont loopfe *Xlf d_U d_D vcont loopfe
* d to a for plotting ** d to a for plotting
abridge-w1 [d_divout d_ref d_Un d_D] [s1 s2 u1 d1] dac1 ; change to d_u or d_Un ** select d_U or d_Un according to loop filter
abridge-w1 [d_divout d_ref d_Un d_D] [s1 s2 u1n d1] dac1
*abridge-w1 [d_divout d_ref d_U d_D] [s1 s2 u1 d1] dac1
.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5 .model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5
+ input_load = 5.0e-12 t_rise = 1e-10 + input_load = 5.0e-12 t_rise = 1e-10 t_fall = 1e-10)
+ t_fall = 1e-10)
.control .control
save cont s1 s2 u1 d1 save vcont s1 s2 u1 d1
iplot cont iplot vcont
* calculate breakpoint for switching frequency ** calculate breakpoint for switching frequency
let t1_3 = simtime/3 let t1_3 = simtime/3
set ti1_3 ="$&t1_3" set ti1_3 ="$&t1_3"
let t2_3 = simtime/3*2 let t2_3 = simtime/3*2
set ti2_3 ="$&t2_3" set ti2_3 ="$&t2_3"
stop when time=$ti1_3 stop when time=$ti1_3
stop when time=$ti2_3 stop when time=$ti2_3
* calculate new periods for f2 ** calculate new periods for f2
let per2=1/f2 let per2=1/f2
let pw2 = per2/2 let pw2 = per2/2
let per3=1/f3 let per3=1/f3
let pw3 = per3/2 let pw3 = per3/2
*simulate ** simulate
tran 0.1n $&simtime uic tran 0.2n $&simtime uic
*change frequency after stopping ** change frequency after stopping
* first pair of [] without spaces, second pair with spaces ** first pair of [] without spaces, second pair with spaces
alter @vref[pulse] = [ 0 3.3 10n 1n 1n $&pw2 $&per2 ] alter @vref[pulse] = [ 0 3.3 10n 1n 1n $&pw2 $&per2 ]
resume resume
*another change after second stop ** another change after second stop
alter @vref[pulse] = [ 0 3.3 10n 1n 1n $&pw3 $&per3 ] alter @vref[pulse] = [ 0 3.3 10n 1n 1n $&pw3 $&per3 ]
resume resume
rusage rusage
plot cont s1 s2+1.2 u1+2.4 d1+3.6 xlimit 15u 16u plot vcont s1 s2+1.2 u1+2.4 d1+3.6 xlimit 15u 16u
*plot cont *plot vcont
.endc .endc
*model = bsim3v3 ** model = bsim3v3
*Berkeley Spice Compatibility ** Berkeley Spice Compatibility
* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20 * Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20
.model N1 NMOS .model N1 NMOS
*+version = 3.2.4 *+version = 3.2.4

74
examples/xspice/pll/pll-xspice.cir
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@ -1,79 +1,79 @@
* pll circuit using xspice code models *** pll circuit using xspice code models
* output frequency 400 MHz ** mixed signal simulation
* locked to a 1 or 10 MHz reference ** output frequency 400 MHz
** locked to a 1 or 10 MHz reference
.param vcc=3.3 .param vcc=3.3
.param divisor=40 .param divisor=40
.param fref=10e6 .param fref=10e6
.csparam simtime=25u .csparam simtime=16u
.global d_d0 d_d1 .global d_d0 d_d1
vdd dd 0 dc 'vcc' vdd dd 0 dc 'vcc'
*vco cont 0 dc 1.9
*PULSE(V1 V2 TD TR TF PW PER) ** reference frequency selected by param fref
* reference frequency selected by param fref ** PULSE(V1 V2 TD TR TF PW PER)
* PULSE(V1 V2 TD TR TF PW PER)
vref ref 0 dc 0 pulse(0 'vcc' 10n 1n 1n '1/fref/2' '1/fref') vref ref 0 dc 0 pulse(0 'vcc' 10n 1n 1n '1/fref/2' '1/fref')
abridgeref [ref] [d_ref] adc_vbuf abridgeref [ref] [d_ref] adc_vbuf
.model adc_vbuf adc_bridge(in_low = 0.5 in_high = 0.5) .model adc_vbuf adc_bridge(in_low = 0.5 in_high = 0.5)
*digital zero ** digital zero
vzero z 0 dc 0 vzero z 0 dc 0
abridgev3 [z] [d_d0] adc_vbuf abridgev3 [z] [d_d0] adc_vbuf
.model adc_vbuf adc_bridge(in_low = 'vcc*0.5' in_high = 'vcc*0.5') .model adc_vbuf adc_bridge(in_low = 'vcc*0.5' in_high = 'vcc*0.5')
*digital one ** digital one
ainv1 d_d0 d_d1 invd1 ainv1 d_d0 d_d1 invd1
.model invd1 d_inverter(rise_delay = 1e-10 fall_delay = 1e-10) .model invd1 d_inverter(rise_delay = 1e-10 fall_delay = 1e-10)
* vco ** vco
* buf: analog out ** buf: analog out
* d_digout: digital out ** d_digout: digital out
* cont: analog control voltage ** vcont: analog control voltage
* dd: analog supply voltage ** dd: analog supply voltage
*.include vco_sub.cir *.include vco_sub.cir
*xvco buf d_digout cont dd ro_vco *xvco buf d_digout vcont dd ro_vco
.include vco_sub_new.cir .include vco_sub_new.cir
xvco buf d_digout cont dd d_osc_vco xvco buf d_digout vcont dd d_osc_vco
* digital divider ** digital divider
adiv1 d_digout d_divout divider adiv1 d_digout d_divout divider
.model divider d_fdiv(div_factor = 'divisor' high_cycles = 'divisor/2' .model divider d_fdiv(div_factor = 'divisor' high_cycles = 'divisor/2'
+ i_count = 4 rise_delay = 1e-10 + i_count = 4 rise_delay = 1e-10
+ fall_delay = 1e-10) + fall_delay = 1e-10)
* frequency phase detector ** frequency phase detector
.include f-p-det-d-sub.cir .include f-p-det-d-sub.cir
Xfpdet d_divout d_ref d_U d_Un d_D d_Dn f-p-det Xfpdet d_divout d_ref d_U d_Un d_D d_Dn f-p-det
* loop filters ** loop filters
*2nd or 3rd order, transistors as switches ** 2nd or 3rd order, transistors as switches
.include loop-filter-2.cir *.include loop-filter-2.cir
Xlf d_Un d_D cont loopf *Xlf d_Un d_D vcont loopf
* 2nd order, Exxxx voltage controlled current sources as 'switches' ** 2nd order, Exxxx voltage controlled current sources as 'switches'
* loop filter current sources as charge pump ** loop filter current sources as charge pump
*.include loop-filter.cir .include loop-filter.cir
*Xlf d_U d_D cont loopfe Xlf d_U d_D vcont loopfe
* d to a for plotting ** d to a for plotting
abridge-w1 [d_divout d_ref d_Un d_D] [s1 s2 u1n d1] dac1 ; change to d_u or d_Un ** select d_U or d_Un according to loop filter
*abridge-w1 [d_divout d_ref d_Un d_D] [s1 s2 u1n d1] dac1
abridge-w1 [d_divout d_ref d_U d_D] [s1 s2 u1n d1] dac1
.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5 .model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5
+ input_load = 5.0e-12 t_rise = 1e-10 + input_load = 5.0e-12 t_rise = 1e-10 t_fall = 1e-10)
+ t_fall = 1e-10)
.control .control
save cont s1 s2 u1n d1 v.xlf.vdd#branch; to save memory save vcont s1 s2 u1n d1 v.xlf.vdd#branch; to save memory
iplot cont iplot vcont
tran 0.1n $&simtime uic tran 0.1n $&simtime uic
rusage rusage
plot cont s1 s2+1.2 u1n+2.4 d1+3.6 xlimit 4u 5u plot vcont s1 s2+1.2 u1n+2.4 d1+3.6 xlimit 4u 5u
plot v.xlf.vdd#branch xlimit 4u 5u ylimit -8m 2m plot v.xlf.vdd#branch xlimit 4u 5u ylimit -8m 2m
*plot cont *plot vcont
.endc .endc
*model = bsim3v3 ** model = bsim3v3
*Berkeley Spice Compatibility ** Berkeley Spice Compatibility
* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20 * Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20
.model N1 NMOS .model N1 NMOS
*+version = 3.2.4 *+version = 3.2.4