Example for 7490a Pspice subckt. This exercises jkff, logicexp, and pindly conversions to XSPICE.
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Brian Taylor
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Conversion of Pspice 7490a decade counters
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* ----------------------------------------------------------- 7490A ------
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* Decade Counters
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*
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* The TTL Logic Data Book, 1988, TI Pages 2-277 to 2-287
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* bss 2/25/94
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*
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.SUBCKT 7490A R01 R02 R91 R92 CKA CKB QA QB QC QD
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+ optional: DPWR=$G_DPWR DGND=$G_DGND
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+ params: MNTYMXDLY=0 IO_LEVEL=0
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U1 JKFF(1) DPWR DGND
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+ NAND9 NAND0 CKA $D_HI $D_HI QA_O $D_NC
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+ D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
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U2 JKFF(1) DPWR DGND
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+ $D_HI NANDC CKB QDBAR $D_HI QB_O $D_NC
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+ D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
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U3 JKFF(1) DPWR DGND
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+ $D_HI NANDC QB_O $D_HI $D_HI QC_O $D_NC
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+ D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
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U4 JKFF(1) DPWR DGND
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+ NAND9 NAND0 CKB ANDQ QD_O QD_O QDBAR
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+ D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
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U5LOG LOGICEXP(6,4) DPWR DGND
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+ R01 R02 R91 R92 QB_O QC_O
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+ NAND9 NAND0 NANDC ANDQ
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+ D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
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+
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+ LOGIC:
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+ NAND0 = {~(R01 & R02)}
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+ NAND9 = {~(R91 & R92)}
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+ NANDC = {NAND0 & NAND9}
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+ ANDQ = {QB_O & QC_O}
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U6DLY PINDLY(4,0,4) DPWR DGND
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+ QA_O QB_O QC_O QD_O
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+ CKA CKB NAND9 NAND0
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+ QA QB QC QD
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+ IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
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+
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+ BOOLEAN:
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+ CHA = {CHANGED_HL(CKA,0)}
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+ CHB = {CHANGED_HL(CKB,0)}
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+ SETTO9 = {CHANGED_HL(NAND9,0)}
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+ SETTO0 = {CHANGED_HL(NAND0,0)}
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+ SET = {SETTO0 | SETTO9}
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+
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+ PINDLY:
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+ QA = {
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+ CASE(
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+ SETTO0 & TRN_HL, DELAY(-1,26ns,40ns),
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+ SETTO9 & TRN_LH, DELAY(-1,20ns,30ns),
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+ CHA & TRN_LH, DELAY(-1,10ns,16ns),
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+ CHA & TRN_HL, DELAY(-1,12ns,18ns),
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+ DELAY(-1,27ns,41ns))}
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+
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+ QB = {
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+ CASE(
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+ SET & TRN_HL, DELAY(-1,26ns,40ns),
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+ CHB & TRN_LH, DELAY(-1,10ns,16ns),
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+ CHB & TRN_HL, DELAY(-1,14ns,21ns),
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+ DELAY(-1,27ns,41ns))}
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+
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+ QC = {
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+ CASE(
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+ SET & TRN_HL, DELAY(-1,26ns,40ns),
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+ CHB & TRN_LH, DELAY(-1,21ns,32ns),
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+ CHB & TRN_HL, DELAY(-1,23ns,35ns),
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+ DELAY(-1,27ns,41ns))}
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+
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+ QD = {
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+ CASE(
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+ SETTO0 & TRN_HL, DELAY(-1,26ns,40ns),
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+ SETTO9 & TRN_LH, DELAY(-1,20ns,30ns),
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+ CHB & TRN_LH, DELAY(-1,21ns,32ns),
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+ CHB & TRN_HL, DELAY(-1,23ns,35ns),
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+ CHA & TRN_LH, DELAY(-1,32ns,48ns),
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+ CHA & TRN_HL, DELAY(-1,34ns,50ns),
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+ DELAY(-1,35ns,51ns))}
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U7CON CONSTRAINT(8) DPWR DGND
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+ R01 R02 R91 R92 CKA CKB NAND9 NAND0
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+ IO_STD IO_LEVEL={IO_LEVEL}
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+
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+ FREQ:
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+ NODE=CKA
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+ MAXFREQ=32MEG
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+
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+ FREQ:
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+ NODE=CKB
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+ MAXFREQ=16MEG
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+
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+ WIDTH:
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+ NODE=CKA
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+ MIN_HI=15ns
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+ MIN_LO=15ns
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+
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+ WIDTH:
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+ NODE=CKB
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+ MIN_HI=30ns
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+ MIN_LO=30ns
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+
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+ WIDTH:
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+ NODE=R01
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+ MIN_HI=15ns
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+ WHEN = {NAND9!='0}
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+
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+ WIDTH:
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+ NODE=R02
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+ MIN_HI=15ns
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+ WHEN = {NAND9!='0}
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+
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+ WIDTH:
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+ NODE=R91
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+ MIN_HI=15ns
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+ WHEN = {NAND0!='0}
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+
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+ WIDTH:
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+ NODE=R92
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+ MIN_HI=15ns
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+ WHEN = {NAND0!='0}
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+
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+ SETUP_HOLD:
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+ CLOCK HL = CKA
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+ DATA(1) = NAND9
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+ SETUPTIME_HI = 25ns
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+ MESSAGE = "SETUP ERROR - R91 R92 SETUP < 25ns"
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+
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+ SETUP_HOLD:
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+ CLOCK HL = CKB
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+ DATA(1) = NAND9
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+ SETUPTIME_HI = 25ns
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+ MESSAGE = "SETUP ERROR - R91 R92 SETUP < 25ns"
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+
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+ SETUP_HOLD:
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+ CLOCK HL = CKA
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+ DATA(1) = NAND0
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+ SETUPTIME_HI = 25ns
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+ WHEN = {NAND9!='0}
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+ MESSAGE = "SETUP ERROR - R01 R02 SETUP < 25ns"
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+
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+ SETUP_HOLD:
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+ CLOCK HL = CKB
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+ DATA(1) = NAND0
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+ SETUPTIME_HI = 25ns
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+ WHEN = {NAND9!='0}
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+ MESSAGE = "SETUP ERROR - R01 R02 SETUP < 25ns"
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.ENDS 7490A
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* .SUBCKT 7490A R01 R02 R91 R92 CKA CKB QA QB QC QD
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* output qa is connected to ckb and clock is applied to cka
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* triggered on falling edge of clka
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x1 r01 r02 r91 r92 clka qa1 qa1 qb1 qc1 qd1 7490a
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* output qd is connected to cka and clock is applied to ckb
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* triggered on falling edge of clkb
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***x2 r01 r02 r91 r92 od2 clkb oa2 ob2 oc2 od2 7490a
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* the outputs are ordered to match the datasheet for the BCD mode
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x2 r01 r02 r91 r92 o2 clkb o1 o4 o3 o2 7490a
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a1 [clka] input_vec1
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.model input_vec1 d_source(input_file = "7490a.clk.stim")
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a2 [clkb] input_vec1
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a3 [r01 r02 r91 r92] input_vec2
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.model input_vec2 d_source(input_file = "7490a.control.stim")
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.save all
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.control
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tran 1ns 6us
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run
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listing r
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eprint r01 r02 r91 r92 clka clkb
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eprint qd1 qc1 qb1 qa1
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eprint o1 o2 o3 o4
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* save data to input directory
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cd $inputdir
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eprvcd r01 r02 r91 r92 clka clkb qd1 qc1 qb1 qa1 o1 o2 o3 o4 > 7490a.vcd
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* plotting the vcd file with GTKWave
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if $oscompiled = 1 | $oscompiled = 8 ; MS Windows
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shell start gtkwave 7490a.vcd --script nggtk.tcl
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else
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if $oscompiled = 7 ; macOS, manual tweaking required (mark, insert, Zoom Fit)
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shell open -a gtkwave 7490a.vcd
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else ; Linux and others
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shell gtkwave 7490a.vcd --script nggtk.tcl &
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end
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end
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*plot qd1 qc1 qb1 qa1 digitop
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*plot o1 o2 o3 o4 digitop
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quit
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.endc
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.end
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@ -0,0 +1,49 @@
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* T c
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* i l
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* m k
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* e
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0ns 1s
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100ns 0s
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200ns 1s
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300ns 0s
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400ns 1s
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500ns 0s
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600ns 1s
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700ns 0s
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800ns 1s
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1000ns 0s
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1200ns 1s
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1400ns 0s
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1600ns 1s
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1800ns 0s
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2000ns 1s
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2200ns 0s
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2400ns 1s
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2600ns 0s
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2800ns 1s
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3000ns 0s
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3200ns 1s
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3400ns 0s
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3600ns 1s
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3800ns 0s
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4000ns 1s
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4200ns 0s
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4400ns 1s
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4600ns 0s
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4800ns 1s
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5000ns 0s
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5200ns 1s
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@ -0,0 +1,9 @@
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* T r r r r
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* i 0 0 9 9
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* m 1 2 1 2
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* e
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0ns 0s 0s 0s 0s
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50ns 0s 0s 1s 1s
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250ns 1s 1s 0s 0s
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450ns 1s 1s 0s 0s
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650ns 0s 0s 0s 0s
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