luke
/
ngspice
mirror of https://git.code.sf.net/p/ngspice/ngspice
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

white spaces

This commit is contained in:
dwarning 2018-10-12 09:59:52 +02:00 committed by Holger Vogt
parent d636f7899b
commit 2b3cfd7727
1 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/spicelib/devices/bsim3v32/b3v32ld.c
View File

@ -2514,18 +2514,18 @@ finished:
czbdswg = model->BSIM3v32unitLengthGateSidewallJctCap
* here->BSIM3v32drainPerimeter;
}
czbdsw = 0.0;
czbdsw = 0.0;
}
else
{
czbdsw = model->BSIM3v32unitLengthSidewallTempJctCap
* (here->BSIM3v32drainPerimeter - pParam->BSIM3v32weff);
czbdswg = model->BSIM3v32unitLengthGateSidewallTempJctCap
* pParam->BSIM3v32weff;
czbdsw = model->BSIM3v32unitLengthSidewallTempJctCap
* (here->BSIM3v32drainPerimeter - pParam->BSIM3v32weff);
czbdswg = model->BSIM3v32unitLengthGateSidewallTempJctCap
* pParam->BSIM3v32weff;
}
if (here->BSIM3v32sourcePerimeter < pParam->BSIM3v32weff)
{
czbssw = 0.0;
czbssw = 0.0;
/* Added revision dependent code */
switch (model->BSIM3v32intVersion) {
case BSIM3v32V324:
@ -2536,7 +2536,7 @@ finished:
case BSIM3v32V322:
case BSIM3v32V32:
default:
czbsswg = model->BSIM3v32unitLengthGateSidewallJctCap
czbsswg = model->BSIM3v32unitLengthGateSidewallJctCap
* here->BSIM3v32sourcePerimeter;
}
}