Merge branch 'pre-master' into bt_dev

This commit is contained in:
Brian Taylor 2023-08-05 09:38:00 -07:00
commit 299d7c0dc6
4 changed files with 6 additions and 7 deletions

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@ -21,7 +21,7 @@ set scratch=$curplot $ store its name to 'scratch'
setplot $scratch $ make 'scratch' the active plot
let ft=unitvec(ft_runs) $ create a vector in plot 'scratch' to store ft data
let ic=unitvec(ft_runs) $ create a vector in plot 'scratch' to store ic data
foreach myic 1m 4m 7m 10m 20m 40m 60m 75m 90m 100m 110m 130m 180m
foreach myic 2m 5m 9m 15m 22m 30m 50m 75m 90m 100m 110m 130m 180m
alter ic = $myic
ac dec 100 100k 50g
*plot vdb(vgain#branch)

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@ -9,7 +9,6 @@ XQ1 C B 0 S qnva
.control
dc vc 0.0 5.0 0.05 ib 1u 10u 1u
run
plot abs(i(vc))
.endc

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@ -1350,10 +1350,9 @@ struct inp_read_t inp_read( FILE *fp, int call_depth, const char *dir_name,
*/
if (ciprefix(".lib", buffer))
if (newcompat.lt || newcompat.ps) {
/* compatibility mode,
* this is neither a libray section definition nor a
* reference interpret as old style .lib <file name> (no lib
* name given)
/* In lt or ps there is no library section definition defined,
* so .lib is interpreted as old style .lib <file name> (no lib
* name given, .lib replaced by .include).
*/
char *s = skip_non_ws(buffer); /* skip over .lib */
fprintf(cp_err, " File included as: .inc %s\n", s);

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@ -246,7 +246,8 @@ VBICload(GENmodel *inModel, CKTcircuit *ckt)
Vrth = 0.0, Icth = 0.0, Icth_Vrth = 0.0;
} else if((ckt->CKTmode & MODEINITJCT) && (here->VBICoff==0)) {
Vbe=Vbei=Vbex=model->VBICtype*here->VBICtVcrit;
Vbc=Vbci=Vbcx=Vbep=0.0;
Vbc=Vbcx=Vbep=0.0;
Vbci=-model->VBICtype*here->VBICtVcrit;
Vbcp=Vbc-Vbe;
Vrci=Vrbi=Vrbp=0.0;
Vrcx=Vrbx=Vre=Vrs=0.0;