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* asrc/asrcset.c, bjt/bjtsetup.c, bsim1/b1set.c, bsim2/b2set.c, 

bsim3/b3set.c, bsim3v2/b3v2set.c, bsim4/b4set.c, ccvs/ccvsset.c,
        dio/diosetup.c, ind/indsetup.c, jfet/jfetset.c, jfet2/jfet2set.c,
        ltra/ltraset.c, mes/messetup.c, mos1/mos1set.c, mos2/mos2set.c,
        mos3/mos3set.c, mos6/mos6set.c, tra/trasetup.c, urc/urcsetup.c,
        vcvs/vcvsset.c, vsrc/vsrcset.c: Removed HAS_BATCHSIM preprocessor
        checks.
This commit is contained in:
arno 2000-08-28 20:07:03 +00:00
parent f2c0cec4c4
commit 2462eb7b01
23 changed files with 58 additions and 87 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/spicelib/devices/ChangeLog
View File

@ -1,3 +1,13 @@
2000-08-28 Arno W. Peters <A.W.Peters@ieee.org>
* asrc/asrcset.c, bjt/bjtsetup.c, bsim1/b1set.c, bsim2/b2set.c,
bsim3/b3set.c, bsim3v2/b3v2set.c, bsim4/b4set.c, ccvs/ccvsset.c,
dio/diosetup.c, ind/indsetup.c, jfet/jfetset.c, jfet2/jfet2set.c,
ltra/ltraset.c, mes/messetup.c, mos1/mos1set.c, mos2/mos2set.c,
mos3/mos3set.c, mos6/mos6set.c, tra/trasetup.c, urc/urcsetup.c,
vcvs/vcvsset.c, vsrc/vsrcset.c: Removed HAS_BATCHSIM preprocessor
checks.
2000-07-21 Arno W. Peters <A.W.Peters@ieee.org>
* README: Updated.

2
src/spicelib/devices/asrc/asrcset.c
View File

@ -147,7 +147,6 @@ ASRCunsetup(inModel,ckt)
GENmodel *inModel;
CKTcircuit *ckt;
{
#ifndef HAS_BATCHSIM
ASRCmodel *model;
ASRCinstance *here;
@ -163,6 +162,5 @@ ASRCunsetup(inModel,ckt)
}
}
}
#endif
return OK;
}

2
src/spicelib/devices/bjt/bjtsetup.c
View File

@ -220,7 +220,6 @@ BJTunsetup(inModel,ckt)
GENmodel *inModel;
CKTcircuit *ckt;
{
#ifndef HAS_BATCHSIM
BJTmodel *model;
BJTinstance *here;
@ -250,6 +249,5 @@ BJTunsetup(inModel,ckt)
}
}
}
#endif
return OK;
}

2
src/spicelib/devices/bsim1/b1set.c
View File

@ -383,7 +383,6 @@ B1unsetup(inModel,ckt)
GENmodel *inModel;
CKTcircuit *ckt;
{
#ifndef HAS_BATCHSIM
B1model *model;
B1instance *here;
@ -407,6 +406,5 @@ B1unsetup(inModel,ckt)
}
}
}
#endif
return OK;
}

2
src/spicelib/devices/bsim2/b2set.c
View File

@ -553,7 +553,6 @@ B2unsetup(inModel,ckt)
GENmodel *inModel;
CKTcircuit *ckt;
{
#ifndef HAS_BATCHSIM
B2model *model;
B2instance *here;
@ -577,6 +576,5 @@ B2unsetup(inModel,ckt)
}
}
}
#endif
return OK;
}

2
src/spicelib/devices/bsim3/b3set.c
View File

@ -967,7 +967,6 @@ BSIM3unsetup(inModel,ckt)
GENmodel *inModel;
CKTcircuit *ckt;
{
#ifndef HAS_BATCHSIM
BSIM3model *model;
BSIM3instance *here;
@ -991,7 +990,6 @@ BSIM3unsetup(inModel,ckt)
}
}
}
#endif
return OK;
}

2
src/spicelib/devices/bsim3v2/b3v2set.c
View File

@ -968,7 +968,6 @@ BSIM3V2unsetup(inModel,ckt)
GENmodel *inModel;
CKTcircuit *ckt;
{
#ifndef HAS_BATCHSIM
BSIM3V2model *model;
BSIM3V2instance *here;
@ -992,6 +991,5 @@ BSIM3V2unsetup(inModel,ckt)
}
}
}
#endif
return OK;
}

2
src/spicelib/devices/bsim4/b4set.c
View File

@ -1586,7 +1586,6 @@ BSIM4unsetup(inModel,ckt)
GENmodel *inModel;
CKTcircuit *ckt;
{
#ifndef HAS_BATCHSIM
BSIM4model *model;
BSIM4instance *here;
@ -1610,6 +1609,5 @@ BSIM4unsetup(inModel,ckt)
}
}
}
#endif
return OK;
}

2
src/spicelib/devices/ccvs/ccvsset.c
View File

@ -70,7 +70,6 @@ CCVSunsetup(inModel,ckt)
GENmodel *inModel;
CKTcircuit *ckt;
{
#ifndef HAS_BATCHSIM
CCVSmodel *model;
CCVSinstance *here;
@ -86,6 +85,5 @@ CCVSunsetup(inModel,ckt)
}
}
}
#endif
return OK;
}

2
src/spicelib/devices/dio/diosetup.c
View File

@ -114,7 +114,6 @@ DIOunsetup(inModel,ckt)
GENmodel *inModel;
CKTcircuit *ckt;
{
#ifndef HAS_BATCHSIM
DIOmodel *model;
DIOinstance *here;
@ -133,6 +132,5 @@ DIOunsetup(inModel,ckt)
}
}
}
#endif
return OK;
}

2
src/spicelib/devices/ind/indsetup.c
View File

@ -68,7 +68,6 @@ INDunsetup(inModel,ckt)
GENmodel *inModel;
CKTcircuit *ckt;
{
#ifndef HAS_BATCHSIM
INDmodel *model;
INDinstance *here;
@ -84,6 +83,5 @@ INDunsetup(inModel,ckt)
}
}
}
#endif
return OK;
}

2
src/spicelib/devices/jfet/jfetset.c
View File

@ -154,7 +154,6 @@ JFETunsetup(inModel,ckt)
GENmodel *inModel;
CKTcircuit *ckt;
{
#ifndef HAS_BATCHSIM
JFETmodel *model;
JFETinstance *here;
@ -178,6 +177,5 @@ JFETunsetup(inModel,ckt)
}
}
}
#endif
return OK;
}

2
src/spicelib/devices/jfet2/jfet2set.c
View File

@ -106,7 +106,6 @@ JFET2unsetup(inModel,ckt)
GENmodel *inModel;
CKTcircuit *ckt;
{
#ifndef HAS_BATCHSIM
JFET2model *model;
JFET2instance *here;
@ -130,6 +129,5 @@ JFET2unsetup(inModel,ckt)
}
}
}
#endif
return OK;
}

2
src/spicelib/devices/ltra/ltraset.c
View File

@ -227,7 +227,6 @@ LTRAunsetup(inModel, ckt)
GENmodel *inModel;
CKTcircuit *ckt;
{
#ifndef HAS_BATCHSIM
LTRAmodel *model;
LTRAinstance *here;
@ -245,6 +244,5 @@ LTRAunsetup(inModel, ckt)
}
}
}
#endif
return OK;
}

2
src/spicelib/devices/mes/messetup.c
View File

@ -140,7 +140,6 @@ MESunsetup(inModel,ckt)
GENmodel *inModel;
CKTcircuit *ckt;
{
#ifndef HAS_BATCHSIM
MESmodel *model;
MESinstance *here;
@ -164,6 +163,5 @@ MESunsetup(inModel,ckt)
}
}
}
#endif
return OK;
}

2
src/spicelib/devices/mos1/mos1set.c
View File

@ -192,7 +192,6 @@ MOS1unsetup(inModel,ckt)
GENmodel *inModel;
CKTcircuit *ckt;
{
#ifndef HAS_BATCHSIM
MOS1model *model;
MOS1instance *here;
@ -216,6 +215,5 @@ MOS1unsetup(inModel,ckt)
}
}
}
#endif
return OK;
}

2
src/spicelib/devices/mos2/mos2set.c
View File

@ -219,7 +219,6 @@ MOS2unsetup(inModel,ckt)
GENmodel *inModel;
CKTcircuit *ckt;
{
#ifndef HAS_BATCHSIM
MOS2model *model;
MOS2instance *here;
@ -243,6 +242,5 @@ MOS2unsetup(inModel,ckt)
}
}
}
#endif
return OK;
}

2
src/spicelib/devices/mos3/mos3set.c
View File

@ -237,7 +237,6 @@ MOS3unsetup(inModel,ckt)
GENmodel *inModel;
CKTcircuit *ckt;
{
#ifndef HAS_BATCHSIM
MOS3model *model;
MOS3instance *here;
@ -261,6 +260,5 @@ MOS3unsetup(inModel,ckt)
}
}
}
#endif
return OK;
}

2
src/spicelib/devices/mos6/mos6set.c
View File

@ -208,7 +208,6 @@ MOS6unsetup(inModel,ckt)
GENmodel *inModel;
CKTcircuit *ckt;
{
#ifndef HAS_BATCHSIM
MOS6model *model;
MOS6instance *here;
@ -232,6 +231,5 @@ MOS6unsetup(inModel,ckt)
}
}
}
#endif
return OK;
}

2
src/spicelib/devices/tra/trasetup.c
View File

@ -122,7 +122,6 @@ TRAunsetup(inModel,ckt)
GENmodel *inModel;
CKTcircuit *ckt;
{
#ifndef HAS_BATCHSIM
TRAmodel *model;
TRAinstance *here;
@ -150,6 +149,5 @@ TRAunsetup(inModel,ckt)
}
}
}
#endif
return OK;
}

93
src/spicelib/devices/urc/urcsetup.c
View File

@ -284,60 +284,63 @@ URCunsetup(inModel,ckt)
GENmodel *inModel;
CKTcircuit *ckt;
{
#ifndef HAS_BATCHSIM
IFuid varUid;
int error;
URCinstance *here;
URCmodel *model = (URCmodel *) inModel;
GENinstance *in;
GENmodel *modfast;
int type;
IFuid varUid;
int error;
URCinstance *here;
URCmodel *model = (URCmodel *) inModel;
GENinstance *in;
GENmodel *modfast;
int type;
/* Delete models, devices, and intermediate nodes;
*/
/* Delete models, devices, and intermediate nodes; */
for ( ; model; model = model->URCnextModel) {
for (here = model->URCinstances; here;
here = here->URCnextInstance)
{
if(model->URCisPerLGiven) {
/* Diodes */
error = (*(SPfrontEnd->IFnewUid))(ckt,&varUid,here->URCname,
"diodemod",UID_MODEL,(void **)NULL);
} else {
/* Capacitors */
error = (*(SPfrontEnd->IFnewUid))((void *)ckt,&varUid,
here->URCname, "capmod",UID_MODEL,(void **)NULL);
}
if (error && error != E_EXISTS)
return error;
for ( ; model; model = model->URCnextModel) {
for (here = model->URCinstances; here;
here = here->URCnextInstance)
{
if(model->URCisPerLGiven) {
/* Diodes */
error = (*(SPfrontEnd->IFnewUid))(ckt, &varUid,
here->URCname,
"diodemod",
UID_MODEL,
(void **)NULL);
} else {
/* Capacitors */
error = (*(SPfrontEnd->IFnewUid))((void *)ckt, &varUid,
here->URCname,
"capmod",
UID_MODEL,
(void **)NULL);
}
if (error && error != E_EXISTS)
return error;
modfast = NULL;
type = -1;
error = CKTfndMod(ckt, &type, (void **) &modfast, varUid);
if (error)
return error;
modfast = NULL;
type = -1;
error = CKTfndMod(ckt, &type, (void **) &modfast, varUid);
if (error)
return error;
for (in = modfast->GENinstances; in; in = in->GENnextInstance)
CKTdltNNum(ckt, in->GENnode1);
for (in = modfast->GENinstances; in; in = in->GENnextInstance)
CKTdltNNum(ckt, in->GENnode1);
CKTdltMod(ckt, modfast); /* Does the elements too */
CKTdltMod(ckt, modfast); /* Does the elements too */
/* Resistors */
error = (*(SPfrontEnd->IFnewUid))(ckt,&varUid,here->URCname,
"resmod",UID_MODEL,(void **)NULL);
if (error && error != E_EXISTS)
return error;
/* Resistors */
error = (*(SPfrontEnd->IFnewUid))(ckt,&varUid,here->URCname,
"resmod",UID_MODEL,(void **)NULL);
if (error && error != E_EXISTS)
return error;
modfast = NULL;
type = -1;
error = CKTfndMod(ckt, &type, (void **) &modfast, varUid);
if (error)
return error;
modfast = NULL;
type = -1;
error = CKTfndMod(ckt, &type, (void **) &modfast, varUid);
if (error)
return error;
CKTdltMod(ckt, modfast);
CKTdltMod(ckt, modfast);
}
}
#endif
return OK;
}

2
src/spicelib/devices/vcvs/vcvsset.c
View File

@ -63,7 +63,6 @@ VCVSunsetup(inModel,ckt)
GENmodel *inModel;
CKTcircuit *ckt;
{
#ifndef HAS_BATCHSIM
VCVSmodel *model;
VCVSinstance *here;
@ -79,6 +78,5 @@ VCVSunsetup(inModel,ckt)
}
}
}
#endif
return OK;
}

2
src/spicelib/devices/vsrc/vsrcset.c
View File

@ -60,7 +60,6 @@ VSRCunsetup(inModel,ckt)
GENmodel *inModel;
CKTcircuit *ckt;
{
#ifndef HAS_BATCHSIM
VSRCmodel *model;
VSRCinstance *here;
@ -76,6 +75,5 @@ VSRCunsetup(inModel,ckt)
}
}
}
#endif
return OK;
}