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various digital simulations of a 4-bit NAND gate full adder: 

Bipolar, MOS, behavioral, and event based
This commit is contained in:
Holger Vogt 2018-07-08 14:20:00 +02:00
parent fac5754b79
commit 1cbcd25cab
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226
examples/digital/74HCng_short_2.lib Normal file
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* 74hcng.lib
*
* derived from 74HCxxx Model libraray for LTSPICE from www.linear.com/software
*
* Revision 1.01 06/25/2018 test devices NAND, NOR, and XOR as XSPICE subcircuit for ngspice
*
* All parts have been divided into three sections.
*
* >--| A-D-Converter (threshold VCC1/2) |----| Event LOGIC Axx (delay) |----| OUTPUT LEVEL D-A (rise and fall times) |-->
*
* Delays are given for Vcc = 2V/4.5V/6V (HC) from the
* Philips data sheets. http://www.philipslogic.com
*
* Delays are given for Vcc = 2V/4.5V/6V .
* Used delay: Td = (Tpd-Tr/2)*(4.5-0.5)/(Vcc-0.5)
* The gate delay has to be set to tpd minus 3ns for the input filter
* and another minus 3ns for Trise/2
* td1 = tpd - 3ns - 3ns
*
.param vcc=5 tripdt=6n
***********************************************************************************
* The 74HCXX gates
*
* 2-input NAND gate
* vcc 2 /4.5/5 /6
* tpd 25n/9n/7n/7n
* tr 19n/7n / /6n
.SUBCKT 74HC00 in1 in2 out NVCC NVGND vcc1={vcc} tripdt1={tripdt}
.param td1={1e-9*(9-3-3)*4.0/(vcc1-0.5)}
.param Rout={60*4.0/(vcc1-0.5)} $ standard output driver
*Cin1 in1 0 3.5p
*Cin2 in2 0 3.5p
abridge2 [in1 in2] [din1 din2] adc_buff
.model adc_buff adc_bridge(in_low = {vcc1/2.0} in_high = {vcc1/2.0})
a6 [din1 din2] dout nand1
.model nand1 d_nand(rise_delay = {td1} fall_delay = {td1}
+ input_load = 0.5e-12)
abridge1 [dout] [out20] dac1
.model dac1 dac_bridge(out_low = 0.0 out_high = {vcc1} out_undef = {vcc1/2.0}
+ input_load = 5.0e-12 t_rise = {tripdt1}
+ t_fall = {tripdt1})
Rout out20 out {Rout}
.ends
* 2-input NOR gate
* tpd 25n/9n/7n
* tr 19n/7n/6n
.SUBCKT 74HC02 in1 in2 out NVCC NVGND vcc1={vcc} tripdt1={tripdt}
.param td1={1e-9*(9-3-3)*4.0/(vcc1-0.5)}
.param Rout={60*4.0/(vcc1-0.5)} $ standard output driver
*Cin1 in1 0 3.5p
*Cin2 in2 0 3.5p
abridge2 [in1 in2] [din1 din2] adc_buff
.model adc_buff adc_bridge(in_low = {vcc1/2.0} in_high = {vcc1/2.0})
a6 [din1 din2] dout nor1
.model nor1 d_nor(rise_delay = {td1} fall_delay = {td1} input_load = 0.5e-12)
abridge1 [dout] [out20] dac1
.model dac1 dac_bridge(out_low = 0.0 out_high = {vcc1} out_undef = {vcc1/2.0}
+ input_load = 5.0e-12 t_rise = {tripdt1} t_fall = {tripdt1})
Rout out20 out {Rout}
.ends
** 2-input AND gate
* tpd 25n/9n/7n
* tr 19n/7n/6n
.SUBCKT 74HC08 in1 in2 out NVCC NVGND vcc1={vcc} tripdt1={tripdt}
.param td1={1e-9*(9-3-3)*4.0/(vcc1-0.5)}
.param Rout={60*4.0/(vcc1-0.5)} $ standard output driver
*Cin1 in1 0 3.5p
*Cin2 in2 0 3.5p
abridge2 [in1 in2] [din1 din2] adc_buff
.model adc_buff adc_bridge(in_low = {vcc1/2.0} in_high = {vcc1/2.0})
a6 [din1 din2] dout and1
.model and1 d_and(rise_delay = {td1} fall_delay = {td1}
+ input_load = 0.5e-12)
abridge1 [dout] [out20] dac1
.model dac1 dac_bridge(out_low = 0.0 out_high = {vcc1} out_undef = {vcc1/2.0}
+ input_load = 5.0e-12 t_rise = {tripdt1}
+ t_fall = {tripdt1})
Rout out20 out {Rout}
.ends
**
* 2-input OR gate
* tpd 25n/9n/7n
* tr 19n/7n/6n
.SUBCKT 74HC32 in1 in2 out NVCC NVGND vcc1={vcc} tripdt1={tripdt}
.param td1={1e-9*(9-3-3)*4.0/(vcc1-0.5)}
.param Rout={60*4.0/(vcc1-0.5)} $ standard output driver
*Cin1 in1 0 3.5p
*Cin2 in2 0 3.5p
abridge2 [in1 in2] [din1 din2] adc_buff
.model adc_buff adc_bridge(in_low = {vcc1/2.0} in_high = {vcc1/2.0})
a6 [din1 din2] dout or1
.model or1 d_or(rise_delay = {td1} fall_delay = {td1} input_load = 0.5e-12)
abridge1 [dout] [out20] dac1
.model dac1 dac_bridge(out_low = 0.0 out_high = {vcc1} out_undef = {vcc1/2.0}
+ input_load = 5.0e-12 t_rise = {tripdt1} t_fall = {tripdt1})
Rout out20 out {Rout}
.ends
* 2-input EXOR gate
* tpd 39n/14n/11n
* tr 19n/7n/6n
.SUBCKT 74HC86 in1 in2 out NVCC NVGND vcc1={vcc} tripdt1={tripdt}
.param td1={1e-9*(14-3-3)*4.0/(vcc1-0.5)}
.param Rout={60*4.0/(vcc1-0.5)} $ standard output driver
*Cin1 in1 0 3.5p
*Cin2 in2 0 3.5p
abridge2 [in1 in2] [din1 din2] adc_buff
.model adc_buff adc_bridge(in_low = {vcc1/2.0} in_high = {vcc1/2.0})
a6 [din1 din2] dout xor3
.model xor3 d_xor(rise_delay = {td1} fall_delay = {td1}
+ input_load = 0.5e-12)
abridge1 [dout] [out20] dac1
.model dac1 dac_bridge(out_low = 0.0 out_high = {vcc1} out_undef = {vcc1/2.0}
+ input_load = 5.0e-12 t_rise = {tripdt1} t_fall = {tripdt1})
Rout out20 out {Rout}
.ends
*
*============================================================================
*
* A hopefully real transistor level based model of the 74HCU04. The model
* comes directly from philips. http://www.philipslogic.com/support/spice/
* This a unbuffered inverter which is often used in LC or crystal oscillators.
* Inverter, unbuffered
* Original Philips model used.
.SUBCKT 74HCU04 A Y VCC VGND vcc1={vcc} speed1={speed} tripdt1={tripdt}
*Rin A A1 200
*Cin A1 VGND 3p
*XAY A1 Y VCC VGND 74HC04_INV0
XAY A Y VCC VGND 74HC04_INV0
.ends
*
*
.SUBCKT 74HC04_INV0 2 3 80 90
*IN=2, OUT=3, VCC=80, GND=90
XINP 20 25 50 60 74HC_INP0N
XOUTP 25 30 50 60 74HC_OUTPN
L1 80 50 6.87NH
L2 60 90 6.87NH
L3 2 20 5.97NH
L4 30 3 5.97NH
C1 50 90 1.5P
C2 60 90 1.5P
C3 20 90 1.5P
C4 3 90 1.5P
.ENDS
*
.SUBCKT 74HC_INP0N 2 3 50 60
*IN=2, OUT=3, VCC=50, GND=60
R1 2 3 100
MP1 3 50 50 50 MHCPEN W=20U L=2.4U AD=100P AS=100P PD=40U PS= 20U
MN1 3 60 60 60 MHCNEN W=35U L=2.4U AD=260P AS=260P PD=70U PS= 20U
.ENDS
*
.SUBCKT 74HC_OUTPN 2 3 50 60
*IN=2, OUT=3, VCC=50, GND=60
R1 2 4 100
MP1 3 4 50 50 MHCPEN W=360U L=2.4U AD=400P AS=400P PD=10U PS=180U
MN1 3 4 60 60 MHCNEN W=140U L=2.4U AD=200P AS=300P PD=10U PS=130U
R2 4 5 50
MP2 3 5 50 50 MHCPEN W=360U L=2.4U AD=400P AS=400P PD=10U PS=180U
MN2 3 5 60 60 MHCNEN W=140U L=2.4U AD=200P AS=200P PD=10U PS=130U
R3 5 6 50
MP3 3 6 50 50 MHCPEN W=360U L=2.4U AD=400P AS=400P PD=10U PS=180U
MN3 3 6 60 60 MHCNEN W=140U L=2.4U AD=200P AS=200P PD=10U PS=130U
.ENDS
************************************************
* NOMINAL N-Channel Transistor *
* UCB-3 Parameter Set *
* HIGH-SPEED CMOS Logic Family *
* 10-Jan.-1995 *
************************************************
.Model MHCNEN NMOS (
+LEVEL = 3
+KP = 45.3E-6
+VTO = 0.72
+TOX = 51.5E-9
+NSUB = 2.8E15
+GAMMA = 0.94
+PHI = 0.65
+VMAX = 150E3
+RS = 40
+RD = 40
+XJ = 0.11E-6
+LD = 0.52E-6
+DELTA = 0.315
+THETA = 0.054
+ETA = 0.025
+KAPPA = 0.0
+WD = 0.0 )
***********************************************
* NOMINAL P-Channel transistor *
* UCB-3 Parameter Set *
* HIGH-SPEED CMOS Logic Family *
* 10-Jan.-1995 *
***********************************************
.Model MHCPEN PMOS (
+LEVEL = 3
+KP = 22.1E-6
+VTO = -0.71
+TOX = 51.5E-9
+NSUB = 3.3E16
+GAMMA = 0.92
+PHI = 0.65
+VMAX = 970E3
+RS = 80
+RD = 80
+XJ = 0.63E-6
+LD = 0.23E-6
+DELTA = 2.24
+THETA = 0.108
+ETA = 0.322
+KAPPA = 0.0
+WD = 0.0 )

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Compare four different 4-bit full adders,
made of NAND gates
Simulating for 6400ns
adder_bib
The old spice bipolar NAND gate full adder
Simulation time 14.0s
adder_mos
A MOS NAND gate inverter, using BSIM3 and OpenMP
Simulation time 10.5s
adder_behav
NAND gates made with XSPICE digital devices,
but each has an analog interface, the interconnect
is analog, gate library is 74HCng_short_2.lib
Simulation time 1.9s
adder_Xspice
Fully digital, event node based NAND gates
digital plotting into vcd file, display with gtkwave
Simulation time 0.27s

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ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER
*** SUBCIRCUIT DEFINITIONS
.SUBCKT NAND in1 in2 out
* NODES: INPUT(2), OUTPUT
a6 [in1 in2] out nand1
.ENDS NAND
.model nand1 d_nand(rise_delay = 0.7e-9 fall_delay = 0.7e-9
+ input_load = 0.5e-12)
.SUBCKT ONEBIT 1 2 3 4 5
* NODES: INPUT(2), CARRY-IN, OUTPUT, CARRY-OUT
X1 1 2 7 NAND
X2 1 7 8 NAND
X3 2 7 9 NAND
X4 8 9 10 NAND
X5 3 10 11 NAND
X6 3 11 12 NAND
X7 10 11 13 NAND
X8 12 13 4 NAND
X9 11 7 5 NAND
.ENDS ONEBIT
.SUBCKT TWOBIT 1 2 3 4 5 6 7 8
* NODES: INPUT - BIT0(2) / BIT1(2), OUTPUT - BIT0 / BIT1,
* CARRY-IN, CARRY-OUT
X1 1 2 7 5 10 ONEBIT
X2 3 4 10 6 8 ONEBIT
.ENDS TWOBIT
.SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14
* NODES: INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2),
* OUTPUT - BIT0 / BIT1 / BIT2 / BIT3, CARRY-IN, CARRY-OUT
X1 1 2 3 4 9 10 13 16 TWOBIT
X2 5 6 7 8 11 12 16 14 TWOBIT
.ENDS FOURBIT
*** ALL INPUTS (analog)
VIN1A a1 0 DC 0 PULSE(0 3 0 0.5NS 0.5NS 20NS 50NS)
VIN1B a2 0 DC 0 PULSE(0 3 0 0.5NS 0.5NS 30NS 100NS)
VIN2A a3 0 DC 0 PULSE(0 3 0 0.5NS 0.5NS 50NS 200NS)
VIN2B a4 0 DC 0 PULSE(0 3 0 0.5NS 0.5NS 90NS 400NS)
VIN3A a5 0 DC 0 PULSE(0 3 0 0.5NS 0.5NS 170NS 800NS)
VIN3B a6 0 DC 0 PULSE(0 3 0 0.5NS 0.5NS 330NS 1600NS)
VIN4A a7 0 DC 0 PULSE(0 3 0 0.5NS 0.5NS 650NS 3200NS)
VIN4B a8 0 DC 0 PULSE(0 3 0 0.5NS 0.5NS 1290NS 6400NS)
*** analog to digital
abridge2 [a1 a2 a3 a4 a5 a6 a7 a8] [1 2 3 4 5 6 7 8] adc_buff
.model adc_buff adc_bridge(in_low = 1 in_high = 2)
*** digital 0
V0 a0 0 0
abridge0 [a0] [d0] adc_buff
*** DEFINE NOMINAL CIRCUIT
X1 1 2 3 4 5 6 7 8 s0 s1 s2 s3 d0 c3 FOURBIT
*.TRAN 500p 6400NS
* save inputs
*.save V(a1) V(a2) V(a3) V(a4) V(a5) V(a6) V(a7) V(a8)
*.save v(1)
.control
*save v(1)
TRAN 500p 6400NS
rusage
display
edisplay
* save data to input directory
cd $inputdir
eprvcd 1 2 3 4 5 6 7 8 s0 s1 s2 s3 c3 > adder_x.vcd
* plotting the vcd file (e.g. with GTKWave)
* For Windows: returns control to ngspice
shell start gtkwave adder_x.vcd --script nggtk.tcl
* Others
*shell gtkwave adder_x.vcd --script nggtk.tcl &
.endc
.END

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ADDER - 4 BIT ALL-74HC00-GATE BINARY ADDER
* behavioral gate description
*** SUBCIRCUIT DEFINITIONS
.include D:\Spice_general\ngspice\examples\digital\74HCng_short_2.lib
.param vcc=3 tripdt=6n
.SUBCKT ONEBIT 1 2 3 4 5 6
* NODES: INPUT(2), CARRY-IN, OUTPUT, CARRY-OUT, VCC
X1 1 2 7 6 0 74HC00
X2 1 7 8 6 0 74HC00
X3 2 7 9 6 0 74HC00
X4 8 9 10 6 0 74HC00
X5 3 10 11 6 0 74HC00
X6 3 11 12 6 0 74HC00
X7 10 11 13 6 0 74HC00
X8 12 13 4 6 0 74HC00
X9 11 7 5 6 0 74HC00
.ENDS ONEBIT
.SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9
* NODES: INPUT - BIT0(2) / BIT1(2), OUTPUT - BIT0 / BIT1,
* CARRY-IN, CARRY-OUT, VCC
X1 1 2 7 5 10 9 ONEBIT
X2 3 4 10 6 8 9 ONEBIT
.ENDS TWOBIT
.SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
* NODES: INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2),
* OUTPUT - BIT0 / BIT1 / BIT2 / BIT3, CARRY-IN, CARRY-OUT, VCC
X1 1 2 3 4 9 10 13 16 15 TWOBIT
X2 5 6 7 8 11 12 16 14 15 TWOBIT
.ENDS FOURBIT
*** POWER
VCC 99 0 DC 3.3V
*** ALL INPUTS
VIN1A 1 0 DC 0 PULSE(0 3 0 5NS 5NS 20NS 50NS)
VIN1B 2 0 DC 0 PULSE(0 3 0 5NS 5NS 30NS 100NS)
VIN2A 3 0 DC 0 PULSE(0 3 0 5NS 5NS 50NS 200NS)
VIN2B 4 0 DC 0 PULSE(0 3 0 5NS 5NS 90NS 400NS)
VIN3A 5 0 DC 0 PULSE(0 3 0 5NS 5NS 170NS 800NS)
VIN3B 6 0 DC 0 PULSE(0 3 0 5NS 5NS 330NS 1600NS)
VIN4A 7 0 DC 0 PULSE(0 3 0 5NS 5NS 650NS 3200NS)
VIN4B 8 0 DC 0 PULSE(0 3 0 5NS 5NS 1290NS 6400NS)
*** DEFINE NOMINAL CIRCUIT
X1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT
.option noinit acct
.TRAN 500p 6400NS
* save inputs
.save V(1) V(2) V(3) V(4) V(5) V(6) V(7) V(8)
.control
pre_set strict_errorhandling
unset ngdebug
*save outputs and specials
save x1.x1.x1.7 V(9) V(10) V(11) V(12) V(13)
run
rusage
* plot the inputs, use offset to plot on top of each other
plot v(1) v(2)+4 v(3)+8 v(4)+12 v(5)+16 v(6)+20 v(7)+24 v(8)+28
* plot the outputs, use offset to plot on top of each other
plot v(9) v(10)+4 v(11)+8 v(12)+12 v(13)+16
.endc
.END

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ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER
*** SUBCIRCUIT DEFINITIONS
.SUBCKT NAND 1 2 3 4
* NODES: INPUT(2), OUTPUT, VCC
Q1 9 5 1 QMOD
D1CLAMP 0 1 DMOD
Q2 9 5 2 QMOD
D2CLAMP 0 2 DMOD
RB 4 5 4K
R1 4 6 1.6K
Q3 6 9 8 QMOD
R2 8 0 1K
RC 4 7 130
Q4 7 6 10 QMOD
DVBEDROP 10 3 DMOD
Q5 3 8 0 QMOD
.ENDS NAND
.SUBCKT ONEBIT 1 2 3 4 5 6
* NODES: INPUT(2), CARRY-IN, OUTPUT, CARRY-OUT, VCC
X1 1 2 7 6 NAND
X2 1 7 8 6 NAND
X3 2 7 9 6 NAND
X4 8 9 10 6 NAND
X5 3 10 11 6 NAND
X6 3 11 12 6 NAND
X7 10 11 13 6 NAND
X8 12 13 4 6 NAND
X9 11 7 5 6 NAND
.ENDS ONEBIT
.SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9
* NODES: INPUT - BIT0(2) / BIT1(2), OUTPUT - BIT0 / BIT1,
* CARRY-IN, CARRY-OUT, VCC
X1 1 2 7 5 10 9 ONEBIT
X2 3 4 10 6 8 9 ONEBIT
.ENDS TWOBIT
.SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
* NODES: INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2),
* OUTPUT - BIT0 / BIT1 / BIT2 / BIT3, CARRY-IN, CARRY-OUT, VCC
X1 1 2 3 4 9 10 13 16 15 TWOBIT
X2 5 6 7 8 11 12 16 14 15 TWOBIT
.ENDS FOURBIT
*** DEFINE NOMINAL CIRCUIT
.MODEL DMOD D
.MODEL QMOD NPN(BF=75 RB=100 CJE=1PF CJC=3PF)
VCC 99 0 DC 5V
VIN1A 1 0 PULSE(0 3 0 10NS 10NS 10NS 50NS)
VIN1B 2 0 PULSE(0 3 0 10NS 10NS 20NS 100NS)
VIN2A 3 0 PULSE(0 3 0 10NS 10NS 40NS 200NS)
VIN2B 4 0 PULSE(0 3 0 10NS 10NS 80NS 400NS)
VIN3A 5 0 PULSE(0 3 0 10NS 10NS 160NS 800NS)
VIN3B 6 0 PULSE(0 3 0 10NS 10NS 320NS 1600NS)
VIN4A 7 0 PULSE(0 3 0 10NS 10NS 640NS 3200NS)
VIN4B 8 0 PULSE(0 3 0 10NS 10NS 1280NS 6400NS)
X1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT
RBIT0 9 0 1K
RBIT1 10 0 1K
RBIT2 11 0 1K
RBIT3 12 0 1K
RCOUT 13 0 1K
*** (FOR THOSE WITH MONEY (AND MEMORY) TO BURN)
.option noinit acct
.TRAN 1NS 6400NS
*.save VIN1A VIN1B VIN2A VIN2B VIN3A VIN3B VIN4A VIN4B
* save inputs
.save V(1) V(2) V(3) V(4) V(5) V(6) V(7) V(8)
* save outputs
.save V(9) V(10) V(11) V(12) V(13)
*.options savecurrents
*.save alli
.control
run
rusage
* plot the inputs, use offset to plot on top of each other
plot v(1) v(2)+4 v(3)+8 v(4)+12 v(5)+16 v(6)+20 v(7)+24 v(8)+28
* plot the outputs, use offset to plot on top of each other
plot v(9) v(10)+4 v(11)+8 v(12)+12 v(13)+16
.endc
.END

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ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER
*** SUBCIRCUIT DEFINITIONS
.SUBCKT NAND in1 in2 out VDD
* NODES: INPUT(2), OUTPUT, VCC
M1 out in2 Vdd Vdd p1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p
M2 net.1 in2 0 0 n1 W=3u L=0.35u pd=9u ad=9p ps=9u as=9p
M3 out in1 Vdd Vdd p1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p
M4 out in1 net.1 0 n1 W=3u L=0.35u pd=9u ad=9p ps=9u as=9p
.ENDS NAND
.SUBCKT ONEBIT 1 2 3 4 5 6
* NODES: INPUT(2), CARRY-IN, OUTPUT, CARRY-OUT, VCC
X1 1 2 7 6 NAND
X2 1 7 8 6 NAND
X3 2 7 9 6 NAND
X4 8 9 10 6 NAND
X5 3 10 11 6 NAND
X6 3 11 12 6 NAND
X7 10 11 13 6 NAND
X8 12 13 4 6 NAND
X9 11 7 5 6 NAND
.ENDS ONEBIT
.SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9
* NODES: INPUT - BIT0(2) / BIT1(2), OUTPUT - BIT0 / BIT1,
* CARRY-IN, CARRY-OUT, VCC
X1 1 2 7 5 10 9 ONEBIT
X2 3 4 10 6 8 9 ONEBIT
.ENDS TWOBIT
.SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
* NODES: INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2),
* OUTPUT - BIT0 / BIT1 / BIT2 / BIT3, CARRY-IN, CARRY-OUT, VCC
X1 1 2 3 4 9 10 13 16 15 TWOBIT
X2 5 6 7 8 11 12 16 14 15 TWOBIT
.ENDS FOURBIT
*** POWER
VCC 99 0 DC 3.3V
*** ALL INPUTS
VIN1A 1 0 DC 0 PULSE(0 3 0 5NS 5NS 20NS 50NS)
VIN1B 2 0 DC 0 PULSE(0 3 0 5NS 5NS 30NS 100NS)
VIN2A 3 0 DC 0 PULSE(0 3 0 5NS 5NS 50NS 200NS)
VIN2B 4 0 DC 0 PULSE(0 3 0 5NS 5NS 90NS 400NS)
VIN3A 5 0 DC 0 PULSE(0 3 0 5NS 5NS 170NS 800NS)
VIN3B 6 0 DC 0 PULSE(0 3 0 5NS 5NS 330NS 1600NS)
VIN4A 7 0 DC 0 PULSE(0 3 0 5NS 5NS 650NS 3200NS)
VIN4B 8 0 DC 0 PULSE(0 3 0 5NS 5NS 1290NS 6400NS)
*** DEFINE NOMINAL CIRCUIT
X1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT
.option noinit acct
.TRAN 500p 6400NS
* save inputs
.save V(1) V(2) V(3) V(4) V(5) V(6) V(7) V(8)
* use BSIM3 model with default parameters
.model n1 nmos level=49 version=3.3.0
.model p1 pmos level=49 version=3.3.0
*.include ./Modelcards/modelcard32.nmos
*.include ./Modelcards/modelcard32.pmos
.control
pre_set strict_errorhandling
unset ngdebug
*save outputs and specials
save x1.x1.x1.7 V(9) V(10) V(11) V(12) V(13)
run
rusage
* plot the inputs, use offset to plot on top of each other
plot v(1) v(2)+4 v(3)+8 v(4)+12 v(5)+16 v(6)+20 v(7)+24 v(8)+28
* plot the outputs, use offset to plot on top of each other
plot v(9) v(10)+4 v(11)+8 v(12)+12 v(13)+16
.endc
.END

10
examples/digital/nggtk.tcl Normal file
View File

@ -0,0 +1,10 @@
# tcl script for gtkwave: show vcd file data created by ngspice
set nfacs [ gtkwave::getNumFacs ]
for {set i 0} {$i < $nfacs } {incr i} {
set facname [ gtkwave::getFacName $i ]
set num_added [ gtkwave::addSignalsFromList $facname ]
}
gtkwave::/Edit/UnHighlight_All
gtkwave::/Time/Zoom/Zoom_Full