luke
/
ngspice
mirror of https://git.code.sf.net/p/ngspice/ngspice
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

full 4 and 8 elements versions

This commit is contained in:
Florian Ballenegger 2020-07-24 15:04:04 +02:00
parent 15c4dba116
commit 1c9c120e0e
7 changed files with 7981 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
src/spicelib/devices/bsim3v32/b3v32ldseq_simd4.c → src/spicelib/devices/bsim3v32/b3v32ldseq_simd4d.c
View File

@ -1,4 +1,3 @@
/**** BSIM3v3.2.4, Released by Xuemei Xi 12/21/2001 ****/
/**********
* Copyright 2001 Regents of the University of California. All rights reserved.
@ -11,12 +10,27 @@
* Modified by Paolo Nenzi 2002 and Dietmar Warning 2003
* Modified by Florian Ballenegger 2020 for SIMD version generation
**********/
/**********
* Modified 2020 by Florian Ballenegger, Anamosic Ballenegger Design
* Distributed under the same license terms as the original code,
* see file "B3TERMS_OF_USE"
**********/
#ifdef USE_OMP
#pragma message "Warning: simd configured without USE_OMP but compiled with - ignored"
#endif
#ifndef NEWCONV
#pragma message "Warning: simd configured for NEWCONV but compiled without - use anyway"
#endif
#ifdef PREDICTOR
#pragma message "Warning: simd configured without PREDICTOR but compiled with - ignored"
#endif
#ifndef OMP_EFFMEM
#pragma message "Warning: simd configured for OMP_EFFMEM but compiled without - use anyway"
#endif
#ifdef NOBYPASS
#pragma message "Warning: simd configured without NOBYPASS but compiled with - ignored"
#endif
{
Vec4d SourceSatCurrent;
@ -368,13 +382,13 @@
int error;
ScalingFactor = 1.0e-9;
ChargeComputationNeeded = ((ckt->CKTmode & (((MODEDCTRANCURVE | MODEAC) | MODETRAN) | MODEINITSMSIG)) || ((ckt->CKTmode & MODETRANOP) && (ckt->CKTmode & MODEUIC))) ? (1) : (0);
vbs = SIMDLOADDATA(0, data);
vgs = SIMDLOADDATA(1, data);
vds = SIMDLOADDATA(2, data);
qdef = SIMDLOADDATA(3, data);
cdhat = SIMDLOADDATA(4, data);
cbhat = SIMDLOADDATA(5, data);
Check = SIMDLOADDATA(6, data) > 0.5;
vbs = vec4_SIMDLOADDATA(0, data);
vgs = vec4_SIMDLOADDATA(1, data);
vds = vec4_SIMDLOADDATA(2, data);
qdef = vec4_SIMDLOADDATA(3, data);
cdhat = vec4_SIMDLOADDATA(4, data);
cbhat = vec4_SIMDLOADDATA(5, data);
Check = vec4_SIMDLOADDATA(6, data) > 0.5;
SIMDIFYCMD(start);
vbd = vbs - vds;
vgd = vgs - vds;

18
src/spicelib/devices/bsim3v32/b3v32ldseq_simd4_omp.c → src/spicelib/devices/bsim3v32/b3v32ldseq_simd4d_omp.c
View File

@ -1,4 +1,3 @@
/**** BSIM3v3.2.4, Released by Xuemei Xi 12/21/2001 ****/
/**********
* Copyright 2001 Regents of the University of California. All rights reserved.
@ -11,12 +10,27 @@
* Modified by Paolo Nenzi 2002 and Dietmar Warning 2003
* Modified by Florian Ballenegger 2020 for SIMD version generation
**********/
/**********
* Modified 2020 by Florian Ballenegger, Anamosic Ballenegger Design
* Distributed under the same license terms as the original code,
* see file "B3TERMS_OF_USE"
**********/
#ifndef USE_OMP
#pragma message "Warning: simd configured for USE_OMP but compiled without - use anyway"
#endif
#ifndef NEWCONV
#pragma message "Warning: simd configured for NEWCONV but compiled without - use anyway"
#endif
#ifndef OMP_EFFMEM
#pragma message "Warning: simd configured for OMP_EFFMEM but compiled without - use anyway"
#endif
#ifdef NOBYPASS
#pragma message "Warning: simd configured without NOBYPASS but compiled with - ignored"
#endif
#ifdef PREDICTOR
#pragma message "Warning: simd configured without PREDICTOR but compiled with - ignored"
#endif
{
Vec4d SourceSatCurrent;

34
src/spicelib/devices/bsim3v32/b3v32ldseq_simd8d.c
View File

@ -1,3 +1,37 @@
/**********
* Copyright 2001 Regents of the University of California. All rights reserved.
* Original File: b3ld.c of BSIM3v3.2.4
* Author: 1991 JianHui Huang and Min-Chie Jeng.
* Modified by Mansun Chan (1995).
* Author: 1997-1999 Weidong Liu.
* Author: 2001 Xuemei Xi
* Modified by Xuemei Xi, 10/05, 12/21, 2001.
* Modified by Paolo Nenzi 2002 and Dietmar Warning 2003
* Modified by Florian Ballenegger 2020 for SIMD version generation
**********/
/**********
* Modified 2020 by Florian Ballenegger, Anamosic Ballenegger Design
* Distributed under the same license terms as the original code,
* see file "B3TERMS_OF_USE"
**********/
#ifndef OMP_EFFMEM
#pragma message "Warning: simd configured for OMP_EFFMEM but compiled without - use anyway"
#endif
#ifdef PREDICTOR
#pragma message "Warning: simd configured without PREDICTOR but compiled with - ignored"
#endif
#ifndef NEWCONV
#pragma message "Warning: simd configured for NEWCONV but compiled without - use anyway"
#endif
#ifdef USE_OMP
#pragma message "Warning: simd configured without USE_OMP but compiled with - ignored"
#endif
#ifdef NOBYPASS
#pragma message "Warning: simd configured without NOBYPASS but compiled with - ignored"
#endif
{
Vec8d SourceSatCurrent;
Vec8d DrainSatCurrent;

7616
src/spicelib/devices/bsim3v32/b3v32ldseq_simd8d_omp.c Normal file
View File

File diff suppressed because it is too large Load Diff

6
src/spicelib/devices/bsim3v32/b3v32ldsimd.c
View File

@ -80,14 +80,14 @@ int BSIM3v32LoadSIMD(BSIM3v32instance **heres, CKTcircuit *ckt
#if NSIMD==4
#ifdef USE_OMP
#pragma message "Use OMP SIMD4 version"
#include "b3v32ldseq_simd4_omp.c"
#include "b3v32ldseq_simd4d_omp.c"
#else
#include "b3v32ldseq_simd4.c"
#include "b3v32ldseq_simd4d.c"
#endif
#elif NSIMD==8
#ifdef USE_OMP
#pragma message "Use OMP SIMD8 version"
#include "b3v32ldseq_simd8_omp.c"
#include "b3v32ldseq_simd8d_omp.c"
#else
#include "b3v32ldseq_simd8d.c"
#endif

289
src/spicelib/devices/bsim3v32/b3v32ldsimd4d.c Normal file
View File

@ -0,0 +1,289 @@
/*******************************************************************************
* Copyright 2020 Florian Ballenegger, Anamosic Ballenegger Design
*******************************************************************************
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
typedef double Vec4d __attribute__ ((vector_size (sizeof(double)*4), aligned (sizeof(double)*4)));
typedef int64_t Vec4m __attribute__ ((vector_size (sizeof(double)*4), aligned (sizeof(double)*4)));
#if USEX86INTRINSICS==1
static inline Vec4d vec4_blend(Vec4d fa, Vec4d tr, Vec4m mask)
{
return _mm256_blendv_pd(fa,tr, (Vec4d) mask);
}
#else
static inline Vec4d vec4_blend(Vec4d fa, Vec4d tr, Vec4m mask)
{
Vec4d r;
//#pragma omp simd
for(int i=0;i<4;i++)
r[i] = (mask[i]==0 ? fa[i] : tr[i]);
return r;
}
#endif
static inline Vec4d vec4_exp(Vec4d x)
{
Vec4d r;
//#pragma omp simd
for(int i=0;i<4;i++)
r[i] = exp(x[i]);
return r;
}
static inline Vec4d vec4_log(Vec4d x)
{
Vec4d r;
//#pragma omp simd
for(int i=0;i<4;i++)
r[i] = log(x[i]);
return r;
}
static inline Vec4d vec4_max(Vec4d x, Vec4d y)
{
Vec4d r;
//#pragma omp simd
for(int i=0;i<4;i++)
r[i] = MAX(x[i],y[i]);
return r;
}
static inline Vec4d vec4_sqrt(Vec4d x)
{
Vec4d r;
//#pragma omp simd
for(int i=0;i<4;i++)
r[i] = sqrt(x[i]);
return r;
}
static inline Vec4d vec4_fabs(Vec4d x)
{
Vec4d r;
//#pragma omp simd
for(int i=0;i<4;i++)
r[i] = fabs(x[i]);
return r;
}
#define vec4_pow0p7(x,p) vec4_pow(x,p)
#define vec4_powMJ(x,p) vec4_pow(x,p)
#define vec4_powMJSW(x,p) vec4_pow(x,p)
#define vec4_powMJSWG(x,p) vec4_pow(x,p)
static inline Vec4d vec4_pow(Vec4d x, double p)
{
return vec4_exp(vec4_log(x)*p);
}
/* useful vectorized functions */
static inline Vec4d vec4_SIMDTOVECTOR(double val)
{
Vec4d r;
//#pragma omp simd
for(int i=0;i<4;i++)
r[i] = val;
return r;
}
static inline Vec4m vec4_SIMDTOVECTORMASK(int val)
{
Vec4m r;
//#pragma omp simd
for(int i=0;i<4;i++)
r[i] = val;
return r;
}
#if 0
static inline Vec4d vec4_SIMDTOVECTOR(double val)
{
return (Vec4d) {val,val,val,val};
}
static inline Vec4m vec4_SIMDTOVECTORMASK(int val)
{
return (Vec4m) {val,val,val,val};
}
#endif
static inline Vec4d vec4_SIMDLOADDATA(int idx, double data[7][4])
{
return (Vec4d) {data[idx][0],data[idx][1],data[idx][2],data[idx][3]};
}
static inline Vec4d vec4_BSIM3v32_StateAccess(double* cktstate, Vec4m stateindexes)
{
Vec4d r;
//#pragma omp simd
for(int i=0;i<4;i++)
r[i] = cktstate[stateindexes[i]];
return r;
/*return (Vec4d) {
cktstate[stateindexes[0]],
cktstate[stateindexes[1]],
cktstate[stateindexes[2]],
cktstate[stateindexes[3]]
};"*/
}
static inline void vec4_BSIM3v32_StateStore(double* cktstate, Vec4m stateindexes, Vec4d values)
{
/*if(0) vec4_CheckCollisions(stateindexes,"SateStore");*/
//#pragma omp simd
for(int idx=0;idx<4;idx++)
{
cktstate[stateindexes[idx]] = values[idx];
}
}
static inline void vec4_BSIM3v32_StateAdd(double* cktstate, Vec4m stateindexes, Vec4d values)
{
/*if(0) vec4_CheckCollisions(stateindexes,"StateAdd");*/
//#pragma omp simd
for(int idx=0;idx<4;idx++)
{
cktstate[stateindexes[idx]] += values[idx];
}
}
static inline void vec4_BSIM3v32_StateSub(double* cktstate, Vec4m stateindexes, Vec4d values)
{
/*if(0) vec4_CheckCollisions(stateindexes,"StateSub");*/
//#pragma omp simd
for(int idx=0;idx<4;idx++)
{
cktstate[stateindexes[idx]] -= values[idx];
}
}
static inline int vec4_BSIM3v32_ACM_saturationCurrents
(
BSIM3v32model *model,
BSIM3v32instance **heres,
Vec4d *DrainSatCurrent,
Vec4d *SourceSatCurrent
)
{
int error;
double dsat,ssat;
for(int idx=0;idx<4;idx++)
{
error = BSIM3v32_ACM_saturationCurrents(
model, heres[idx],
&dsat,
&ssat
);
(*DrainSatCurrent)[idx] = dsat;
(*SourceSatCurrent)[idx] = ssat;
if(error) return error;
}
return error;
}
static inline int vec4_BSIM3v32_ACM_junctionCapacitances(
BSIM3v32model *model,
BSIM3v32instance **heres,
Vec4d *areaDrainBulkCapacitance,
Vec4d *periDrainBulkCapacitance,
Vec4d *gateDrainBulkCapacitance,
Vec4d *areaSourceBulkCapacitance,
Vec4d *periSourceBulkCapacitance,
Vec4d *gateSourceBulkCapacitance
)
{
int error;
double areaDB,periDB,gateDB,areaSB,periSB,gateSB;
for(int idx=0;idx<4;idx++)
{
error = BSIM3v32_ACM_junctionCapacitances(
model, heres[idx],
&areaDB,
&periDB,
&gateDB,
&areaSB,
&periSB,
&gateSB
);
(*areaDrainBulkCapacitance)[idx]=areaDB;
(*periDrainBulkCapacitance)[idx]=periDB;
(*gateDrainBulkCapacitance)[idx]=gateDB;
(*areaSourceBulkCapacitance)[idx]=areaSB;
(*periSourceBulkCapacitance)[idx]=periSB;
(*gateSourceBulkCapacitance)[idx]=gateSB;
if(error) return error;
}
return error;
}
/* geq, ceq, and zero are not translated to vectors because there are unused */
static inline int vec4_NIintegrate(CKTcircuit* ckt, double* geq, double *ceq, double zero, Vec4m chargestate)
{
int error;
/*if (0) vec4_CheckCollisions(chargestate, "NIIntegrate");*/
for(int idx=0;idx<4;idx++)
{
error = NIintegrate(ckt,geq,ceq,zero,chargestate[idx]);
if(error) return error;
}
return error;
}
static inline int vec4_SIMDCOUNT(Vec4m mask) {
return (mask[0] ? 1 : 0) + (mask[1] ? 1 : 0) + (mask[2] ? 1 : 0) + (mask[3] ? 1 : 0);
}
/* some debug utils functions */
void vec4_printd(const char* msg, const char* name, Vec4d vecd)
{
printf("%s %s %g %g %g %g\n",msg,name,vecd[0],vecd[1],vecd[2],vecd[3]);
}
void vec4_printm(const char* msg, const char* name, Vec4m vecm)
{
printf("%s %s %ld %ld %ld %ld\n",msg,name,vecm[0],vecm[1],vecm[2],vecm[3]);
}
void vec4_CheckCollisions(Vec4m stateindexes, const char* msg)
{
for(int i=0;i<4;i++)
for(int j=0;j<4;j++)
if(i!=j)
if(stateindexes[i]==stateindexes[j])
{
printf("%s, collisions %ld %ld %ld %ld!\n",msg,stateindexes[0],stateindexes[1],stateindexes[2],stateindexes[3]);
raise(SIGINT);
}
}

26
src/spicelib/devices/bsim3v32/b3v32ldsimd8d.c
View File

@ -28,32 +28,6 @@
* POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
#include <math.h>
#include <x86intrin.h>
#include <signal.h>
#include "ngspice/ngspice.h"
#include "ngspice/cktdefs.h"
#include "bsim3v32def.h"
#include "b3v32acm.h"
#include "ngspice/trandefs.h"
#include "ngspice/const.h"
#include "ngspice/sperror.h"
#include "ngspice/devdefs.h"
#include "ngspice/suffix.h"
#define MAX_EXP 5.834617425e14
#define MIN_EXP 1.713908431e-15
#define EXP_THRESHOLD 34.0
#define EPSOX 3.453133e-11
#define EPSSI 1.03594e-10
#define Charge_q 1.60219e-19
#define DELTA_1 0.02
#define DELTA_2 0.02
#define DELTA_3 0.02
#define DELTA_4 0.02
typedef double Vec8d __attribute__ ((vector_size (sizeof(double)*8), aligned (sizeof(double)*8)));
typedef int64_t Vec8m __attribute__ ((vector_size (sizeof(double)*8), aligned (sizeof(double)*8)));