Fix typo in vlnggen error message.

2025-04-18 08:25:40 +01:00 · 2025-04-18 08:25:40 +01:00 · 0a224fa704
parent 4881b29730
commit 0a224fa704
1 changed files with 1 additions and 1 deletions
--- a/src/xspice/verilog/vlnggen
+++ b/src/xspice/verilog/vlnggen
@ -342,7 +342,7 @@ else
   if $fh > 0
     fclose $fh
   else
-      echo Can not find bulid file $msvcfile
+      echo Can not find build file $msvcfile
      quit
   end