ngspice/examples/xspice/verilator/delay.v

`timescale 1us/100ns

module delay(out);
   output reg [4:0] out;
   reg		    t;

   initial out = 0;
   always begin
      #1;
      t = out[4];
      out <<= 1;
      out[0] = ~t;
   end
endmodule; // delay
Add additional examples of Verilog co-simulation and share the Verilog source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking. 2024-06-10 12:40:37 +02:00			`timescale 1us/100ns

			`module delay(out);`
			`output reg [4:0] out;`
			`reg t;`

			`initial out = 0;`
			`always begin`
			`#1;`
			`t = out[4];`
			`out <<= 1;`
			`out[0] = ~t;`
			`end`
			`endmodule; // delay`