108 lines
2.5 KiB
Plaintext
108 lines
2.5 KiB
Plaintext
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* This file is not intended to be used directly, but by adc.cir.
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* That allows it to be shared by different implemnetations.
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* Simulation of a switched-capacitor SAR ADC with Verilator and d_cosim
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.subckt sar_adc input vref start valid d5 d4 d3 d2 d1 d0 clk
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* A transmission gate connects the input to the capacitor set.
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xsample input iin sample vref tgate
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rin iin test_v 1k
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* Capacitors and controlling inverters
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xb5 test_v vref d5 ccap c=1p
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xb4 test_v vref d4 ccap c={1p / 2}
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xb3 test_v vref d3 ccap c={1p / 4}
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xb2 test_v vref d2 ccap c={1p / 8}
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xb1 test_v vref d1 ccap c={1p / 16}
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xb0 test_v vref d0 ccap c={1p / 32}
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clast test_v 0 {1p / 32}
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* An XSPICE ADC bridge functions as a comparator.
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acomp [%vd(test_v vref)] [comp] comparator
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.model comparator adc_bridge in_low=0 in_high=0
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* The digital portion of the circuit is specified in compiled Verilog.
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* Outputs inverted to cancel the inverter in subcircuit ccap,
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* and produce the correct numerical output value. The model definition
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* is supplied by the calling circuit file.
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adut [ Clk Comp Start] [Sample Valid ~d5 ~d4 ~d3 ~d2 ~d1 ~d0] dut
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.ends // SUBCKT sar_adc
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* Some MOS transistors complete the circuit.
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* Models from https://homepages.rpi.edu/~sawyes/AIMSPICE_TutorialManual.pdf
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.model p1 pmos
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+ level=2 vto=-0.5 kp=8.5e-6 gamma=0.4 phi=0.65 lambda=0.05 xj=0.5e-6
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.model n1 nmos
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+ level=2 vto=0.5 kp=24e-6 gamma=0.15 phi=0.65 lambda=0.015 xj=0.5e-6
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* Use those for an inverter.
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.subckt ainv in out vdd
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mn out in 0 0 n1
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mp out in vdd vdd p1
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.ends
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* A transmission gate modelled by a switch.
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.subckt mos_tgate a b ctl vdd
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mn a ctl b b n1
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xinv ctl ictl vdd ainv
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mp b ictl a a p1
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.ends
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.subckt tgate a b ctl vdd
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switch a b ctl 0 tg
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.model tg sw vt=1.5 ron=2k
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.ends
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* The per-bit subcircuit in the adc
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.subckt ccap in vcc ctl c=10p
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xinv ctl tail vcc ainv
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cb in tail {c}
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.ends
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**** End of the ADC and its subcircuits. Begin test circuit ****
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.param vcc=3.3
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vcc vcc 0 {vcc}
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* Digital clock signal
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aclock 0 clk clock
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.model clock d_osc cntl_array=[-1 1] freq_array=[1Meg 1Meg]
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* A simple DAC so that the result may be compared to the input.
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r5 d5 sum 2
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r4 d4 sum 4
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r3 d3 sum 8
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r2 d2 sum 16
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r1 d1 sum 32
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r0 d0 sum 64
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vamm sum 0 0
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* Pulse the Start signal high for 1.3uS each 10uS
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Vpulse Start 0 PULSE 0 {vcc} 0.2u 10n 10n 1.3u 10u
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Vtest input 0 PULSE 0 3 0 200u 200u 1u 401u
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* The ADC for testing
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xtest input vcc start valid d5 d4 d3 d2 d1 d0 clk sar_adc
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.control
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tran 100n 250u
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plot input xtest.test_v vamm#branch clk/2 start/3 xtest.sample/3 valid
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.endc
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.end
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